A5101729291- Ferroelectric and Negative Capacitance Devices
- Semiconductor materials and devices
- Advanced Memory and Neural Computing
- Magnetic properties of thin films
- Photorefractive and Nonlinear Optics
- Advanced Fiber Laser Technologies
- Photonic and Optical Devices
- Advancements in Semiconductor Devices and Circuit Design
- Low-power high-performance VLSI design
- Parallel Computing and Optimization Techniques
- Advanced Data Storage Technologies
- 3D IC and TSV technologies
- Additive Manufacturing and 3D Printing Technologies
- Photoreceptor and optogenetics research
- Wireless Power Transfer Systems
- Advancements in Photolithography Techniques
- Optical Wireless Communication Technologies
- Copper Interconnects and Reliability
- Wireless Body Area Networks
- Bluetooth and Wireless Communication Technologies
- Urban Planning and Governance
- Quantum Dots Synthesis And Properties
- Spectroscopy and Chemometric Analyses
- Molecular Communication and Nanonetworks
- Smart Agriculture and AI
Taiwan Semiconductor Manufacturing Company (Taiwan)
2011-2024
Stanford University
2019
National Taiwan University
2002-2015
Intel (United States)
2014-2015
University of Washington
2009-2013
Feng Chia University
2010
Taiwan Semiconductor Manufacturing Company (United States)
2010
National Yang Ming Chiao Tung University
2004
National Sun Yat-sen University
2002
From the cloud to edge devices, artificial intelligence (AI) and machine learning (ML) are widely used in many cognitive tasks, such as image classification speech recognition. In recent years, research on hardware accelerators for AI devices has received more attention, mainly due advantages of at edge: including privacy, low latency, reliable effective use network bandwidth. However, traditional computing architectures (such CPUs, GPUs, FPGAs, even existing accelerator ASICs) cannot meet...
Novel modification of the TiO<sub>2</sub>/CH<sub>3</sub>NH<sub>3</sub>PbI<sub>3</sub>interface using glycine as a coupling agent induced higher coverage perovskite through two-step solution process.
Embedded non-volatile memory (eNVM) is an essential element for microcontrollers (MCUs) used in automotive applications. As the market transitions to greater electrification and autonomy, we are seeing MCU growth car: including integration simplify system design, electrical electronic (E/E) architectural evolution domain/zone control, over-the-air (OTA) updates beyond 128Mb eNVM densities. To support this transition technology nodes migrating from 55/40nm 28/16nm. In addition, traditional...
We present a fully integrated dc-dc converter for micropower energy harvesting. A 1.2- μW bandgap-referenced output controller provides regulation at 1.4 V, achieving quiescent power of 3 and maximum overall efficiency 58% 11 power. modified four-phase charge pump 3× voltage boost minimum input 270 mV in free-running mode. Using dual switches driven from both the output, chip achieves without external excitation or components.
1T1R spin-transfer-torque (STT) MRAM is a promising candidate for next-generation high-density embedded non-volatile memory [1-2]. However, STT-MRAM suffers from limited sensing margin and high write power. As shown in Fig. 30.2.1(a), sense amplifier design challenging due to the small difference (only 2x) between high-resistance state (R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">AP</sub> ) low-resistance...
STT-MRAM is a promising solution for next-generation embedded non-volatile memory (NVM), supporting wide range of applications. Compared to traditional Flash [1]–[2], CMOS-compatible low-temperature back-end-of-the-line (BEOL) memory, requiring only 2-to-5 extra masks. It byte-alterable NVM with excellent write speed, endurance (>1M cycles), and high-temperature data retention capability. In this work, 32Mb using 0.0456µm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML"...
We demonstrate high yield results from a solder-reflow-capable spin-transfer-torque MRAM embedded in 22nm ultra-low leakage (ULL) CMOS technology. The technology supports -40 to 150°C operation and data retention though six solder reflow cycles far exceeding 10 years at 150°C. Ten year native magnetic field immunity is >1100 Oe 25°C the 1ppm bit upset level. A shield-in-package solution demonstrates <; rates disc magnet providing 3.5 kOe disturb exposure for ~80 hours 25°C. Trading off...
A digitally-controlled fully integrated voltage regulator (IVR) enables wide autonomous DVFS in a 22 nm graphics execution core. Part of the original power header is converted into hybrid stage to support digital low-dropout (DLDO), and switched-capacitor (SCVR) modes, addition bypass sleep modes. Using sensing, tunable replica circuit, or core warning signal, IVR detects quickly responds fast droops dynamic workload changes without performance degradation. In prototype, 3D powered up by...
Recently SRAM-based digital compute-in memory (D-CIM) [1] has demonstrated excellent energy/area efficiency, with full precision of 4b/8b integer multiply-accumulate operations, it better programmability, hardware reuse and scalability, in addition, can effectively leverage technology scaling for PPA. Nonetheless, several new challenges remain, including huge peak currents resulting from high parallel operation, long delays adder trees, scalable architectures that support various neural...
We present the design of an ultra-low power, wireless pressure/temperature sensing device for continuous intraocular pressure monitoring. The is wirelessly powered and demonstrates a power consumption 2.3 μW at 1.5 V during chip converts both capacitance temperature to frequency using time-interleaved relaxation oscillator, which modulates RF backscatter reader computation measured samples. A significant reduction in results from elimination digitization circuitry, time-multiplexed...
Technology challenges and solutions in the development fabrication of high-density three dimensional (3D) chip integration structures have been investigated. Critical 3D integrated circuit (IC) enabling technologies, such as through silicon via (TSV), wiring redistribution layer (RDL), wafer thinning handling, micro-bump (μ-bump) processes joining, that form building blocks for IC technology were developed based on established Si foundry technologies. Test vehicles (TV's) designed to develop...
We present the first demonstration of 1T4R Resistive RAM (RRAM) array storing two bits per RRAM cell. Our HfO <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> - based is built using a logic foundry technology that fully compatible with CMOS back-end process. new approach to program cells gradual SET/RESET pulses while minimizing disturbances on adjacent (belonging same structure) this makes our multiple-bits-per-cell possible. report over...
In this paper, we present the design and silicon characterization results of an 8Mb STT-MRAM macro in 16nm FinFET Logic CMOS process. The film stack is carefully designed to achieve both solder-reflow tolerance short write pulse 50nS. A merged reference scheme with reverse connected cells are proposed for read-disturb immunity. read access time 9nS achieved from -40C 125C Vdd=0.8V±10%, making it suitable high performance MCU applications. Silicon data measurement presented demonstrate a...
This paper presents an integrated True Random Number Generator (TRNG) based on the random switching behavior of Magnetic Tunnel Junctions (MTJs) under low write current. A complete TRNG is designed with minimal overhead to existing embedded MRAM in 28nm CMOS. To best our knowledge, this first experimental study process and implemented commercial STT-MRAM technology. The prototype adds only 180μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML"...
1T1MTJ spin-transfer-torque (STT)-MRAM is a promising candidate for next-generation high-density embedded non-volatile memory. This paper presents 1-Mb 28-nm STT-MRAM with improved sensing margin and reduced power consumption. An offset-cancelled sense amplifier proposed, using only single capacitor, to improve accelerate read speed. To save write power, an in situ write-self-termination method proposed where the reconfigured without area overhead continuously monitor operation shutoff...
A new MRAM reference and sensing circuit that can achieve <;±1 μA resolution 17.5 nS read access from -40 °C to 125 is presented in this paper. trimmable current-mode latch-type sense amplifier (CLSA) with hybrid-resistance-reference (HRR) cell location compensation proposed resolve small margin of MRAM. Silicon data measurement demonstrate a logic-process compatible, fully functional 16-Mb perpendicular 40-nm CMOS process. Similar design concept be applied other technology nodes. Another...
We demonstrate a 1MBit array of 1-Transistor-8-Resistive RAM (1T8R) memory fabricated using foundry logic technology. Using gradual SET/RESET programming scheme, sixteen conductance levels are stored in each RRAM, achieving 1T8R with 4 bits per RRAM. report endurance 100K cycles and 10-year retention at 110°C.
A graphics execution core in 22nm improves energy efficiency across a wide DVFS range, from the near-threshold voltage (NTV) region, where circuit assist lowers intrinsic V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">M!N</inf> , to turbo adaptive clocking reduces voltage-droop guard-band [1]. When powered with shared rail, however, is wasted if other blocks demand higher and performance. Alternately, per-core fully-integrated regulator (VR)...
Emerging Memory such as STT-MRAM, RRAM and PCRAM, are attractive candidates to replace the conventional flash memory for embedded applications. The key challenges of these new concepts include small read window, large write current, endurance data retention. Moreover, retention during process soldering reflow (260°C/90s), wafer-level chip-scale package (WLCSP, 340°C/3 hours) magnetic field interference STT-MRAM additional NVM concepts. To address challenges, several design solutions based on...
STT-MRAM has been demonstrated as a viable embedded non-volatile memory (NVM) with 20-year data retention at 150°C, high write endurance (>1M cycles), and the ability to tolerate solder reflow [1]. However, for working applications, even higher endurance, fast speed, small size are necessary. By optimizing magnetic-tunnel-junction (MTJ) stack lower current, while relaxing requirements (e.g., 1 min @ 125°C), can achieve (>10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML"...
We report the synthesis of nonlinear photonic crystals (NPCs) with a periodical distribution inverted χ(2) nonlinearity having an orthorhombic lattice structure on Z-cut congruent-grown lithium niobate (LiNbO3) substrate. The quasiphase-matching (QPM) mechanism wave interaction is examined by monitoring far-field emission pattern second-harmonic generation (SHG) as NPC pumped Nd:yttritium–aluminum–garnet laser beam. observe (i) series green SHG in direction transverse to fundamental beam,...
The demand for high-performance graphics capability even in extremely power-constrained platforms such as smartphones and tablets requires circuit techniques that scale from efficient operation at low voltage to high performance when needed. It is well known energy efficiency improves supply scaled down, reaching a maximum near the device threshold where switching savings reduction balanced by increased leakage frequency loss. Achieving this reduction, however, address intrinsic V <inf...
MRAM can play a variety of on-chip memory roles in advanced VLSI technology spanning from high retention, solder-reflow-capable non-volatile (NVM) to dense or retention working RAMs. This paper describes results for NVM and extensions that trade off against speed, power, density.
The dark current in the active-pixel-sensor (APS) cell of a CMOS imager is known to be mainly generated regions bird's beak after local oxidation silicon process as well surface damage caused by implantation high doping concentration. Furthermore, shallow and deep pn-junctions can improve photo-sensitivity for light short long wavelengths, respectively. In this paper, two new photodiode structures using p-substrate lightly-doped sensor implant SN- pn-junction with embraced p-field implants,...
MRAM can play a variety of on-chip memory roles in advanced VLSI technology spanning from high retention, solder-reflow-capable non-volatile (NVM) to dense or retention working RAMs. This paper describes results for NVM and extensions that trade off against speed, power, density.