Dimitrios Stamoulis

ORCID: 0000-0003-1682-9350
Publications
Citations
Views
---
Saved
---
About
Contact & Profiles
Research Areas
  • Advanced Neural Network Applications
  • Semiconductor materials and devices
  • Machine Learning and Data Classification
  • Adversarial Robustness in Machine Learning
  • Domain Adaptation and Few-Shot Learning
  • Advancements in Semiconductor Devices and Circuit Design
  • Big Data and Business Intelligence
  • Parallel Computing and Optimization Techniques
  • Business Process Modeling and Analysis
  • CCD and CMOS Imaging Sensors
  • Information Technology Governance and Strategy
  • Machine Learning and ELM
  • Ferroelectric and Negative Capacitance Devices
  • Service-Oriented Architecture and Web Services
  • Neural Networks and Applications
  • Advanced Memory and Neural Computing
  • Digital Rights Management and Security
  • Advanced Computational Techniques and Applications
  • Brain Tumor Detection and Classification
  • Information Systems Theories and Implementation
  • E-Government and Public Services
  • Multimedia Communication and Technology
  • Advanced Database Systems and Queries
  • Radiation Effects in Electronics
  • Advanced Surface Polishing Techniques

Microsoft (United States)
2022-2024

National and Kapodistrian University of Athens
2001-2024

University of West Attica
2020-2024

Carnegie Mellon University
2016-2020

Microsoft Research (United Kingdom)
2020

IMEC
2018

McGill University
2014-2016

National Technical University of Athens
2014

Alpha Marine (Greece)
2002

"How much energy is consumed for an inference made by a convolutional neural network (CNN)?" With the increased popularity of CNNs deployed on wide-spectrum platforms (from mobile devices to workstations), answer this question has drawn significant attention. From lengthening battery life reducing bill datacenter, it important understand efficiency during serving making inference, before actually training model. In work, we propose NeuralPower: layer-wise predictive framework based sparse...

10.48550/arxiv.1710.05420 preprint EN other-oa arXiv (Cornell University) 2017-01-01

While selecting the hyper-parameters of Neural Networks (NNs) has been so far treated as an art, emergence more complex, deeper architectures poses increasingly challenges to designers and Machine Learning (ML) practitioners, especially when power memory constraints need be considered. In this work, we propose HyperPower, a framework that enables efficient Bayesian optimization random search in context power- memory-constrained hyperparameter for NNs running on given hardware platform....

10.23919/date.2018.8341973 article EN Design, Automation & Test in Europe Conference & Exhibition (DATE), 2015 2018-03-01

As convolutional neural networks (CNNs) enable state-of-the-art computer vision applications, their high energy consumption has emerged as a key impediment to deployment on embedded and mobile devices. Towards efficient image classification under hardware constraints, prior work proposed adaptive CNNs, i.e., systems of with different accuracy computation characteristics, where selection scheme adaptively selects the network be evaluated for each input image. While previous efforts have...

10.1145/3240765.3240796 article EN 2018-11-05

Governments are employing modern information and communication technologies to serve society better. Raising the effectiveness quality of government services is not only a matter new technologies; it also involves clear vision objectives as well sound business strategy. Information systems need support internal work within government’s boundaries, customers through digital interfaces leverage relationships among social partners. To implement such systems, preparatory required in both...

10.1108/09685220110400327 article EN Information Management & Computer Security 2001-10-01

Recent breakthroughs in Machine Learning (ML) applications, and especially Deep (DL), have made DL models a key component almost every modern computing system. The increased popularity of applications deployed on wide-spectrum platforms (from mobile devices to datacenters) resulted plethora design challenges related the constraints introduced by hardware itself. "What is latency or energy cost for an inference Neural Network (DNN)?" "Is it possible predict this consumption before model even...

10.1145/3240765.3243479 article EN 2018-11-05

Can we reduce the search cost of Neural Architecture Search (NAS) from days down to only few hours? NAS methods automate design Convolutional Networks (ConvNets) under hardware constraints and they have emerged as key components AutoML frameworks. However, problem remains challenging due combinatorially large space significant time (at least 200 GPU-hours). In this work, alleviate less than 3 hours, while achieving state-of-the-art image classification results mobile latency constraints. We...

10.1109/jstsp.2020.2971421 article EN publisher-specific-oa IEEE Journal of Selected Topics in Signal Processing 2020-02-03

We present GeoLLM-Squad, a geospatial Copilot that introduces the novel multi-agent paradigm to remote sensing (RS) workflows. Unlike existing single-agent approaches rely on monolithic large language models (LLM), GeoLLM-Squad separates agentic orchestration from task-solving, by delegating RS tasks specialized sub-agents. Built open-source AutoGen and GeoLLM-Engine frameworks, our work enables modular integration of diverse applications, spanning urban monitoring, forestry protection,...

10.48550/arxiv.2501.16254 preprint EN arXiv (Cornell University) 2025-01-27

Power and thermal issues are the main constraints for high-performance multi-core systems. As current technology of choice, FinFET is observed to have lower delay under higher temperature in super-threshold voltage region, an effect called inversion (TEI). While it has been shown that system performance can be improved power constraints, as aggressively scales down sub-20nm nodes, also emerge important reliability concerns throughout lifetime. To best our knowledge, we first provide a...

10.1145/2966986.2967039 article EN 2016-10-18

Modern many-core systems must cope with a wide range of heterogeneity due to both manufacturing process variations and extreme requirements multi-application, multithreaded workloads. The latter is increasingly challenging in the context different performance constraints per application. Existing thread mapping methods primarily focus on maximizing under global power budget, failing provide thread- application-specific guarantees. This paper provides comprehensive approach for variation-...

10.1145/2934583.2934641 article EN Proceedings of the International Symposium on Low Power Electronics and Design 2016-07-29

Internal and external business forces, mature premature technologies, innovations, new methods of work constitute a multi-dimensional space in which IT organizations have to navigate order present consistent, coherent effective priorities list that need invest to. Despite their importance, these not been systematically investigated but remain at an opinion’s survey level processing. Moreover, modification year by make them less popular subject study. However, review discussion as much...

10.24018/ejbmr.2022.7.1.1225 article EN European Journal of Business Management and Research 2022-01-25

As power density emerges as the main constraint for many-core systems, controlling consumption under thermal design while maximizing performance becomes increasingly critical. To dynamically save power, dynamic voltage frequency scaling techniques have proved to be effective and are widely available commercially. Meanwhile, systems certain constraints that applications should satisfy ensure quality of service. In this paper, we present an online distributed reinforcement learning...

10.1109/tcad.2017.2772822 article EN publisher-specific-oa IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 2017-11-13

10.1145/3649476.3658784 article EN Proceedings of the Great Lakes Symposium on VLSI 2022 2024-06-10

10.1109/cvprw63382.2024.00063 article EN 2022 IEEE/CVF Conference on Computer Vision and Pattern Recognition Workshops (CVPRW) 2024-06-17

Can we automatically design a Convolutional Network (ConvNet) with the highest image classification accuracy under latency constraint of mobile device? Neural Architecture Search (NAS) for ConvNet is challenging problem due to combinatorially large space and search time (at least 200 GPU-hours). To alleviate this complexity, propose Single-Path NAS, novel differentiable NAS method designing device-efficient ConvNets in less than 4 hours. 1. Novel formulation: our introduces single-path,...

10.48550/arxiv.1905.04159 preprint EN other-oa arXiv (Cornell University) 2019-01-01

Prior art on Bias Temperature Instability (BTI) and Random Telegraph Noise (RTN) shows their importance for digital system reliability. Reaction-diffusion models align poorly with deca-nanometer dimension experiments. Modern atomistic capture time-zero/-dependent effects but are complicated constrained by memory. We propose an BTI/RTN transient simulator that can be massively threaded across any many-core platform a hypervisor. Compared to commercial reference we achieve x7 maximum speedup...

10.1109/icicdt.2014.6838587 article EN 2014-05-01

Atomistic-based approaches accurately model Bias Temperature Instability phenomena, but they suffer from prolonged execution times, preventing their seamless integration in system-level analysis flows. In this paper we present a comprehensive flow that combines the accuracy of Capture Emission Time (CET) maps with efficiency Compact Digital Waveform (CDW) representation. That way, capture true workload-dependent BTI-induced degradation selected CPU components. First, show existing works...

10.1145/2902961.2902992 article EN 2016-05-13

In this paper, we propose EDA methodologies for efficient, datapath-wide reliability analysis under Bias Temperature Instability (BTI). The proposed flow combines the efficiency of atomistic, pseudo-transient BTI modeling with accuracy commercial Static Timing Analysis (STA) tools. order to reduce transistor inventory that needs be tracked by STA solver, develop a threshold-pruning methodology identify variation-critical part design. That way, accelerate variation-aware iterations, maximum...

10.1145/2742060.2742079 article EN 2015-05-19

Recent breakthroughs in Deep Learning (DL) applications have made DL models a key component almost every modern computing system. The increased popularity of deployed on wide-spectrum platforms resulted plethora design challenges related to the constraints introduced by hardware itself. What is latency or energy cost for an inference Neural Network (DNN)? Is it possible predict this consumption before model trained? If yes, how can machine learners take advantage these hardware-optimal DNN...

10.48550/arxiv.1809.05476 preprint EN other-oa arXiv (Cornell University) 2018-01-01
Coming Soon ...