A5087726615- Semiconductor materials and devices
- Advancements in Semiconductor Devices and Circuit Design
- Integrated Circuits and Semiconductor Failure Analysis
- Low-power high-performance VLSI design
- Ferroelectric and Negative Capacitance Devices
- VLSI and Analog Circuit Testing
- 3D IC and TSV technologies
- Advanced Memory and Neural Computing
- Advancements in Photolithography Techniques
- Parallel Computing and Optimization Techniques
- Electrostatic Discharge in Electronics
- Copper Interconnects and Reliability
- VLSI and FPGA Design Techniques
- Radiation Effects in Electronics
- Quantum and electron transport phenomena
- Electromagnetic Compatibility and Noise Suppression
- Silicon Carbide Semiconductor Technologies
- Advanced Data Storage Technologies
- Power Line Communications and Noise
- Neural Networks and Reservoir Computing
- Microfluidic and Capillary Electrophoresis Applications
- Nanofabrication and Lithography Techniques
- Thin-Film Transistor Technologies
- Physical Unclonable Functions (PUFs) and Hardware Security
- Text Readability and Simplification
IMEC
2016-2025
KU Leuven
2012-2020
TU Wien
2017
The complementary FET (CFET) device consisting of a stacked n-type vertical sheet on p-type fin is evaluated in design-technology co-optimization (DTCO) framework. Through double level access it offers structural scaling both standard cells (SDC) and SRAM by 50%. proposed process flow requires accurate control the elevation dimension for manufacturability. Based TCAD analysis, CFET can eventually outperform finFET meet N3 targets power performance. To achieve that, dominating parasitic...
In this paper, we show how 5.5 tracks standard cells can be enabled at gate pitch 42 nm and metal 21 achieve 60% active power reduction from the 7nm node. A device downselection methodology driven by performance targets is introduced. This method demonstrates that three stacked nanosheets of 20 width are competitive with FinFETs made two fins while relaxing constraints on layout design rules.
To compensate for expected gate pitch scaling slowdown below 42nm, several boosters are needed to reduce the logic standard cell height (CH). However, limited benefits can be achieved using FinFET and Gate all around (GAA) nanosheets (NSHs) due integration limits in achieving tight PMOS NMOS (PN) separation. Therefore, a novel forksheet (FSH) device architecture is proposed extremely scaled PN space additional processing complexity. The FSH achieves 10% frequency increase at iso-power 24%...
Scaling beyond 5nm will bring us into the post FinFET era where new device architectures optimized for CMOS logic scaling be required. In this paper, evolution to vertically stacked Nanosheets, Forksheet, and finally CFET are reviewed in conjunction with buried power rails wrap around contact. Performance area impact of these evaluated both at standard cell as well block level provide realistic PPA estimate true technology scaling.
The structure of the complementary FET (CFET) with NMOS stacked on top PMOS, inherently yields standard cells and SRAM 25% smaller layout area, higher pin density 2× routing flexibility than FinFET same overall active footprint. Moreover, our work, based advanced modelling, demonstrates that 4 track CFET can match even outperform 5 FinFET; without need to lower S/D contact resistivity down 5e-10Ω.cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML"...
SRAM bitcell area reduction, lower parasitic resistance, and higher drive strength are necessary to continue with technology scaling. Nanosheet (NSH) improves cell write-ability by having 50 mV more write trip point (WTP) than FinFET (FF) due reduced bit line (BL) resistance (due wider metal CD) current (more 15%) FF for the same leakage. However, (20% larger), BL, word (WL) capacitance FF, NSH would not compete in terms of read delay (26% delay) energy at 3-nm node. PFET NFET (PN) spacing,...
This article explores and evaluates six-transistor static random access memory (SRAM) bitcell design options for sequential monolithic complementary field-effect transistors (CFET) in 5-Å-compatible (A5) 3-Å-compatible (A3) technology. A5 CFET offers up to 55% 40% SRAM area scaling due stacked architecture as compared 14-Å-compatible (A14) nanosheet (NS) technology 10-Å-compatible (A10) forksheet (FS) counterparts, respectively. A dielectric isolation wall (DIW) between gates is introduced...
In deeply scaled CMOS technology, time-dependent degradation mechanisms (TDDMs), such as Bias Temperature Instability (BTI), have threatened the transistor performance, hence overall circuit/system reliability. Two well-known attempts to model BTI mechanism are reaction-diffusion (R-D) and Atomistic trap-based model. This paper presents a thorough comparative analysis of two models at gate-level in order explore when their predictions same not. The comparison is done by evaluating trends set...
Despite a number of recent advances made in understanding bias temperature instability (BTI), there is still no simple simulation methodology available which can capture the impact BTI degradation on deeply scaled transistors, while incorporating widely distributed defect parameters. We present physics-based defect-controlled for projecting property distributions into circuit lifetime and performance distributions. This allows evaluating entire population traps (from fast to slow recoverable...
This paper describes the implications of bias temperature instability (BTI)-induced time-dependent threshold voltage distributions on performance and yield estimation digital circuits. The statistical encompassing both time-zero variability their correlations are discussed. impact using normally distributed voltages, imposed by state-of-the-art design approaches, is contrasted with our defect-centric approach. Extensive Monte Carlo simulation results shown for static random access memory...
Here we show that nFET and pFET time-dependent variability, in addition to the standard time-zero can be fully characterized projected using a series of measurements on large test element group (TEG) fabricated an advanced High-k/Metal Gate (HK/MG) technology, thus allowing us characterize underlying technology. BTI is shown follow bimodal defect-centric behavior, for NBTI related Interface Layer (IL)(SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML"...
The continued physical feature size scaling of CMOS transistors is experiencing asperities due to several factors (physical, technological, and economical), it expected reach its boundary in the coming years. Sequential-3D (S3D) integration has been perceived as a promising alternative continue benefits offered by semiconductor scaling. This paper addresses different variants S3D potential challenges achieve realizable solution. We analyze quantify observed sequential at die level.
This paper discusses SRAM scaling beyond the 5nm technology node and highlights fundamental limits due to FinFET Gate all-around (GAA) technology. To compensate for expected gate pitch slowdown below 42nm, several boosters are needed reduce cell height. However, limited benefits can be achieved in GAA Therefore, a novel vertically stacked lateral nanosheet architecture using forked structure is proposed showing superior performance area compared devices. Moreover, additional processing...
Complementary field-effect transistor (CFET) has successfully boosted the area scaling of static random access memory (SRAM) bitcell due to its stacked architecture. However, this architecture introduces taller via connection from frontside back-end-of-line (BEOL) signals bottom pass-gate devices, resulting in increased bitline (BL) and wordline (WL) capacitances ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math...
Channel hot carrier (CHC) stress is observed to result in higher variability of degradation deeply-scaled nFinFETs than bias temperature instability (BTI) stress. Potential sources this increased variation are discussed and the intrinsic time-dependent component extracted using a novel methodology based on matched pairs. It concluded that devices, CHC-induced distributions will be bimodal, pertaining bulk charging interface defect generation, respectively. The latter, high-impact mode...
The CMOS technology scaling faced over the past recent decades severe variability and reliability challenges. One of major challenges is bias temperature instability (BTI). This paper analyzes impact BTI on sensing delay standard latch-type sense amplifier (SA), which one critical components high performance memories; analysis done by incorporating process, voltage, variations (in order to investigate severity integral impact) considering different workloads four nodes (i.e., 45, 32, 22, 16...
We look at several scaling boosters necessary to accomplish CMOS area towards the 2nm node. consider aspects of standard cell scaling, transistor architecture, SRAM, and BEOL. also demonstrate integrated flows hardware feasibility for such boosters.
This letter proposes for the first time buried powered static random-access memory (SRAM) to achieve enhanced write margin and performance in advanced CMOS technology nodes. The power rail (BPR) SRAM is silicon verified. BPR helps lower bitline wordline resistance by relaxing metal width circuits thereby enhances performance. proposed provides up 340 mV 30.6% improvement read speed, respectively, as compared its conventional counterpart without incurring any area penalty a hardware...
This paper evaluates the impact of backside power delivery on physical implementation a commercial 64-bit high-performance block from ARM™ at A14 node. A BEOL, including TSV connections, is proposed and calibrated using TCAD experimental data. The developed stack modeled in cell-level parasitic extraction tool to enable its use during place route. same benchmark physically implemented imec's own PDK. PDN enables frequency improvements 2% 6% compared frontside PDN, stemming core area...
3D vertical poly-Si channel SONOS devices are emerging as the most prominent alternative for 10nm nonvolatile memory technology node and beyond (1–2) provided that a significant drive current I <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">READ</inf> is delivered at fixed reading gate voltage V . Recently, we showed discrete drops observed in transfer characteristic (I xmlns:xlink="http://www.w3.org/1999/xlink">D</inf> vs....