A5065113949- Semiconductor materials and devices
- Advancements in Semiconductor Devices and Circuit Design
- Integrated Circuits and Semiconductor Failure Analysis
- Ferroelectric and Negative Capacitance Devices
- Semiconductor materials and interfaces
- Silicon and Solar Cell Technologies
- Nanowire Synthesis and Applications
- Thin-Film Transistor Technologies
- 3D IC and TSV technologies
- Copper Interconnects and Reliability
- Semiconductor Quantum Structures and Devices
- Advancements in Photolithography Techniques
- Silicon Carbide Semiconductor Technologies
- Metal and Thin Film Mechanics
- Advanced Surface Polishing Techniques
- Electrostatic Discharge in Electronics
- Silicon Nanostructures and Photoluminescence
- Electronic and Structural Properties of Oxides
- Low-power high-performance VLSI design
- Electron and X-Ray Spectroscopy Techniques
- Advanced Memory and Neural Computing
- Photonic and Optical Devices
- Advanced X-ray Imaging Techniques
- Advanced Electron Microscopy Techniques and Applications
- Advanced Semiconductor Detectors and Materials
IMEC
2016-2025
Iwate University
2024
Victoria University of Bangladesh
2023
Analog Devices (United States)
2023
Universität der Bundeswehr München
2023
Shanghai Institute for Science of Science
2023
MIT World Peace University
2023
National Taiwan University
2023
Angstrom Designs (United States)
2023
Imec the Netherlands
2011-2022
We report on gate-all-around (GAA) n- and p-MOSFETs made of 8-nm-diameter vertically stacked horizontal Si nanowires (NWs). show that these devices, which were fabricated bulk substrates using an industry-relevant replacement metal gate (RMG) process, have excellent short-channel characteristics (SS = 65 mV/dec, DIBL 42 mV/V for L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> 24 nm) at performance levels comparable to finFET reference...
We report on the CMOS integration of vertically stacked gate-all-around (GAA) silicon nanowire MOSFETs, with matched threshold voltages (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t, sat</sub> ~ 0.35 V) for N- and P-type devices. The Vt setting is enabled by nanowire-compatible dual-work-function metal in a high-k last replacement gate process. Furthermore, we demonstrate that junction formation can influence release differently due to...
The complementary FET (CFET) device consisting of a stacked n-type vertical sheet on p-type fin is evaluated in design-technology co-optimization (DTCO) framework. Through double level access it offers structural scaling both standard cells (SDC) and SRAM by 50%. proposed process flow requires accurate control the elevation dimension for manufacturability. Based TCAD analysis, CFET can eventually outperform finFET meet N3 targets power performance. To achieve that, dominating parasitic...
We report on CMOS-integrated vertically stacked gate-all-around (GAA) Si nanowire (NW) MOSFETs with in-situ doped source-drain stressors and dual work function metal gates. demonstrate that oxidation-induced SiGe/Si fin deformation by STI densification is effectively suppressed a SiN liner. This protection improves the controllability of formation. In addition, highly-selective nano-wire release inner spacer cavity formation without re-flow are demonstrated. Finally, for first time we...
Next-generation nano and quantum devices have increasingly complex 3D structure. As the dimensions of these shrink to nanoscale, their performance is often governed by interface quality or precise chemical dopant composition. Here we present first phase-sensitive extreme ultraviolet imaging reflectometer. It combines excellent phase stability coherent high-harmonic sources, unique chemical- phase-sensitivity reflectometry, state-of-the-art ptychography algorithms. This tabletop microscope...
With each new node, cost and complexity of logic technology increases while being challenged to provide the historical expected improvement in performance. This paper reviews latest trends advances enable scaling. Dimensional scaling, enabled by EUV lithography, will continue with multi-patterning. Higher costs multi-patterning be mitigated high (0.55) numerical aperture (NA) simplifying patterning potentially leading higher yield. Logic standard cell scaling below 6-track (6T) adequate...
To compensate for expected gate pitch scaling slowdown below 42nm, several boosters are needed to reduce the logic standard cell height (CH). However, limited benefits can be achieved using FinFET and Gate all around (GAA) nanosheets (NSHs) due integration limits in achieving tight PMOS NMOS (PN) separation. Therefore, a novel forksheet (FSH) device architecture is proposed extremely scaled PN space additional processing complexity. The FSH achieves 10% frequency increase at iso-power 24%...
We report extensive statistical NBTI reliability measurements of nanoscaled FETs different technologies, based on which we propose a 1/area scaling rule for the impact individual charged gate oxide defects electrical characteristic deeply scaled transistors. Among considered SiGe channel devices show smallest time-dependent variability. Furthermore, comprehensive trapped charges entire FET ID-VG characteristic. Comparing with 3D atomistic device simulations, identify several behaviors...
The channel hot carrier degradation mechanisms in n-FinFET devices are studied. In long devices, interface by carriers mainly degrades the device at maximum impact ionization condition (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> ~ V xmlns:xlink="http://www.w3.org/1999/xlink">D</sub> /2). At higher closer to , cold and injection oxide bulk defect increases dominates =V stress condition. On other hand, short generated continuously...
We report on vertically stacked gate-all-around (GAA) Si nanowire (NW) MOSFETs, integrated in a CMOS dual Work Function Metal Replacement Gate (RMG) flow. The integration of lower temperature STI module and SiN liner, designed to mitigate the oxidation-induced NW size loss improve width/height aspect ratio controllability, is validated electrically. Additionally, GAA devices with reduced vertical spacing are demonstrated. challenges terms thickness scaling highlighted, thinner nMetal process...
Accurate determination of contact resistivities ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${\rho_{c}}$ </tex-math></inline-formula> ) below notation="LaTeX">$1 \times 10^{-8}\Omega \cdot \text {cm}^{2}$ is challenging. Among the frequently applied transmission line models (TLMs), circular TLM (CTLM) has a simple process flow, while refined (RTLM) high notation="LaTeX">$\rho _{c}$ accuracy at expense...
We report the first monolithic integration of 3D Complementary Field Effect Transistor (CFET) on 300mm wafers using imec's N14 platform. A CFET process is cost effective compared to a sequential process. The small N/P separation in results lower parasitics and higher performance gains. In this paper, fabrication flow, we demonstrate functional PMOS FinFET bottom devices NMOS nanosheet FET top devices. Process development all critical modules enable these are presented. Monolithic scheme...
We study the properties of a single gate oxide trap subjected to AC Bias Temperature Instability (BTI) stress conditions by means Time Dependent Defect Spectroscopy. A theory for predicting occupancy after is developed based on first order kinetics and verified experimental data. The can be used develop circuit simulators predict time dependent variability.
By optimizing design rules, layout, devices and parasitics, we show how 5 Tracks standard cells with one fin can be enabled. This reduces area by 16% without pitch scaling provides 34% energy gain from 6T cells. The loss in speed of 15% recovered different front-end solutions. Air gap spacers are the most efficient booster provide an extra energy. Lateral Nanowires compete FinFETs 12% if tight vertical 10 nm between wires achieved.
N-channel FETs with ferroelectric (FE) HfZrO gate oxide are fabricated, showing steep subthreshold slope under certain conditions. Possible origins of I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</sub> -V xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> hysteresis, the hysteresis versus tradeoff, dependence on bias voltage and temperature competition between trapping FE behavior reported discussed. A band active traps in layer...
The performance of n-type silicon nanosheets, nanowires, and FinFETs is benchmarked by Monte Carlo (MC) device simulation. Measurements nanowire transfer characteristics are provided to validate the MC model supplemented a corresponding comparison for nanosheets with literature data. At an OFF-current per effective gate width 10 nA/μm, ON-currents FinFETs, 500, 545, 570 μA/μm, respectively. A major reason this inferior found be stronger impact surface roughness scattering in nanowires due...
We demonstrate Si-cap-free SiGe p-channel FinFETs and gate-all-around (GAA) FETs in a replacement metal gate (RMG) process, for Ge contents of 25% 45%. show that the performance these devices is substantially improved by high-pressure (HP) deuterium (D <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> ) anneal, which ascribed to 2x reduction interface trap density xmlns:xlink="http://www.w3.org/1999/xlink">IT</sub> ). Furthermore, it found...
In recent CMOS technology, extreme shrinking of contact area at source/drain regions raises serious concerns high metal/semiconductor resistance. Confronting this problem, we introduce a precontact amorphization implantation plus Ti silicidation technique (PCAI + TiSi <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> ) and achieve ultralow resistivity (ρ xmlns:xlink="http://www.w3.org/1999/xlink">c</sub> (1.3 - 1.5) × 10 <sup...
We report on Si nanosheet monolithic Complementary Field-Effect Transistors (CFETs) at industry-relevant 48nm gate pitch, with source-drains (SDs) and SD contacts formed for either bottom or top devices. epi patterning 30nm vertical N-P space high-aspect-ratio contact formation are successfully demonstrated. Functional devices excellent subthreshold slope $(SS_{SAT}=7075$ mV/dec) reported devices, both N- PMOS. Middle dielectric isolation (MDI) by SiGe replacement processing is introduced as...
The metal resistance in the transmission line model (TLM) structures creates a serious obstacle to determine precisely intrinsic contact resistivity. To tackle this problem, we propose new model, lump evaluate influence both TLM and circular (CTLM) test structures. In letter, demonstrate high simplicity, great robustness, flexibility of model. previous reported resistivity values extracted with CTLM are usually above 1 χ 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML"...
Uniaxial stressors have received much interest over the last few years as a method to enhance carrier mobility and, hence, drive current with minimal modification structure of transistor. However, shift in device design complex structures multiple crystallographic orientations like advanced bulk-FinFETs has significantly complicated incorporation enhancing stressors. For n-FinFET particular, it turns out that crystal quality and growth rate Si:P Si:C:P films can be strongly dependent upon...
Record-low contact resistivity (pc) for n-Si, down to 1.5×10−9 Q-cm2, is achieved on Si:P epitaxial layer. We confirm that Ti silicidation reduces the pc while an additional Ge pre-amorphization implantation (PAI) before further extends reduction. In situ doped with P concentration of 2×1021 cm−3 used as substrate, and dynamic surface anneal (DSA) boosts activation. addition, TiOx based metal-insulator-semiconductor (MIS) also studied but found suffer from low thermal stability.
This work discusses the thermal stability of metal-insulator-semiconductor (MIS) contacts. A case study is performed on a typical low-Schottky barrier height (qφb) MIS contact: Ti/TiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /n-Si. By incorporating different levels donor concentration in n-Si, we perform systematic /n-Si under electron conduction mechanisms. We find that both qφ xmlns:xlink="http://www.w3.org/1999/xlink">b</sub>...
As contact resistance becomes a bottle-neck in scaled CMOS devices, there is need for source/drain epitaxy with maximum dopant concentrations and optimized contacting schemes. In this paper we discuss the use of highly doped Si:P layers Source/Drain formation Si bulk FinFETs. We report on macroscopic microscopic properties details microstructure manifestation Phosphorus-Vacancy complexes at high Phosphorus concentrations. analyze how post-epi thermal budget like spike or laser annealing...