A5076321988- CCD and CMOS Imaging Sensors
- Thin-Film Transistor Technologies
- Image Processing Techniques and Applications
- 3D IC and TSV technologies
- Advanced Memory and Neural Computing
- Infrared Target Detection Methodologies
- Neuroscience and Neural Engineering
- Analytical Chemistry and Sensors
- Advanced Optical Sensing Technologies
- Semiconductor materials and devices
- Embedded Systems Design Techniques
- Copper Interconnects and Reliability
- Industrial Vision Systems and Defect Detection
- Advanced MEMS and NEMS Technologies
- Silicon Nanostructures and Photoluminescence
- Advancements in Semiconductor Devices and Circuit Design
- Advanced Fluorescence Microscopy Techniques
- Photonic and Optical Devices
- Sensor Technology and Measurement Systems
- Advanced Surface Polishing Techniques
- Nanofabrication and Lithography Techniques
- Evolutionary Algorithms and Applications
Sony (Taiwan)
2006-2019
Sony Computer Science Laboratories
2019
We have successfully mass-produced novel stacked back-illuminated CMOS image sensors (BI-CIS). In the new CIS, we introduced advanced Cu2Cu hybrid bonding that had developed. The electrical test results showed our highly robust achieved remarkable connectivity and reliability. performance of sensor was also investigated BI-CIS favorable results.
Rolling-shutter CMOS image sensors (CISs) are widely used [1,2]. However, the distortion of moving subjects remains an unresolved problem, regardless speed at which these operated. It has been reported that by adopting in-pixel analog memory (MEM) in pixels, a global shutter (GS) can be achieved saving all pixels simultaneously as stored charges [3,4]. signals from storage unit read column-wise sequence, light-shielding structure is required for MEM to suppress influence parasitic light...
We developed a CMOS image sensor (CIS) chip, which is stacked pixel/DRAM/logic. In this CIS three Si substrates are bonded together, and each substrate electrically connected by two-stacked through-silica vias (TSVs) through the or dynamic random access memory (DRAM). obtained low resistance, leakage current, high reliability characteristics of these TSVs. Connecting metal with TSVs DRAM can be used as resistance wiring for power supply. The thinned to 3 pm, its retention operation...
We have successfully mass-produced novel stacked back-illuminated CMOS image sensors (BI-CIS). In the new CIS, we introduced advanced CuCu hybrid bonding that had developed. The electrical test results showed our highly robust achieved remarkable connectivity and reliability.
In this paper, we report on a back-illuminated, global shutter, CMOS image sensor (CIS) with pixel-parallel, single-slope analog-to-digital converter (ADC). We adopted digital bucket relay transfer multistage flip-flop connection, pixel unit Cu-Cu and positive-feedback circuitry, to realize 6.9-μm pixel-pitch, 1.46-Mpixel pixel-parallel ADC. By operating the comparator bias current in subthreshold region of 7.74-111 nA, succeeded reducing peak during simultaneous combination an ADC standby...
A 1280×960 floating diffusion storage global shutter image sensor is implemented in a 3D stacked back illuminated indirect time of flight (iToF). The sensor, achieves 18,000e- full well capacity and 32% quantum efficiency (QE) with pyramid surface for diffraction (PSD) structure [1], utilizing 3.5µm pixel. Low power consumption also achieved, due to low leakage current the iToF pixel resistance Cu-Cu connection metal wiring. These device architectures enable high resolution wide dynamic...
This paper presents a 4.1 megapixel, 280 frames/s, back-illuminated, stacked, global shutter (GS) CMOS image sensor with array-parallel analog-to-digital converter (ADC) architecture for region-control applications. The solves an distortion problem caused by rolling in pixel sub-array utilizing floating diffusion (FD) memory to implement GS operation. A newly developed circuit technique, the combination of active reset and frame correlated double sampling (CDS) operation, cancels Vth...
We have successfully improved the scaling of Cu-Cu hybrid bonding. In this study, 3 um-pitch and 3M connections with sufficient electrical properties reliabilities were achieved. The ultra-fine pitch correspond to 0.75x conventional bonding that we previously reported. Our high density 3D chip stacking technology is expected enhance not only function back-illuminated CMOS image sensors (BI-CIS) but also coming stacked semiconductor devices.
Currently, there are two coding trends in mobile image sensors: Quad Bayer (QBC) and dual photodiode (DPD). QBC realizes high resolution dynamic range (HDR), whereas DPD achieves phase detection auto focus (PDAF) performance. We propose a with 2×2 on-chip lens (2×2OCL) architecture as potential next-generation high-performance CMOS sensor. This combines resolution, HDR, PDAF performance one The critical issues of 2×2OCL degradation the due to sensitivity difference between 4 pixels under...
A 4.1Mpix 280fps stacked CMOS image sensor with array-parallel ADC architecture is developed for region control applications. The combination of an active reset scheme and frame correlated double sampling (CDS) operation cancels Vth variation pixel amplifier transistors kTC noise. utilizes a floating diffusion (FD) based back-illuminated (BI) global shutter (GS) 4.2e-rms readout An intelligent system face detection high resolution region-of-interest (ROI) output demonstrated significantly...
For the first time, 2-Fin non-doped Pixel-Fin field-effect-transistors are introduced into a 2-Layer Transistor Pixel stacked CMOS image sensor for better noise performance. Thanks to channel and wider width, 2.42-time transconductance improvement, 15% random 99.3% telegraph signal reductions obtained.
In this paper, we propose a 3D stacked global shutter CMOS image sensor with 3M Cu-Cu connections. Using fine pitch and large number of connection technology, achieved 1.46M pixels size 6.9 μm × μm. The pixel evaluation results reveal that all the connections were realized without defect.
In recent years, imaging quality of a CMOS image sensor (CIS) is remarkably improving. This paper reviews the technology development CIS for mobile devices.
We have adapted Cu interconnect layers to realize a high sensitivity in small-pixel CMOS image sensor with pixel size of 2.5 × μm. used the 1P3M process, and applied Back End Line (BEOL) design rule equivalent 90-nm process. The process features fill factor that is about 15% greater an layer height 40% less than those Al As result, at F5.6 5% greater, while F1.2 30% greater. One problems stopper film interferes light. Furthermore, this interacts SiO 2 form multilayer, which leads...