This brief presents the new simple schematic for temperature stable current references based on wellknown β-multiplier circuit. The proposed reference utilizes only four MOS transistors and two lateral PNP transistors, which are usually available in standard CMOS technologies along with one well resistor. temperature-compensation technique has a low process dependence needs no trimming. However, resistor trimming can be used to precisely set output value. circuit implementation of was...

The impact of the reset energy on overall efficiency an successive‐approximation register (SAR) ADC is examined for some recently reported switching schemes. can several times exceed drawn from reference during conversion. simple method based optimal capacitor charging proposed. By utilising two‐step phase, total consumption DAC's capacitive matrix be decreased by ∼20%.

This paper presents two new compact current reference circuits for use in extended industrial range from -45 °C to 125 °C. The first circuit implements very simple order correction. parameters can be obtained by relatively calculations. is well suited generation of currents equal several μA. measurement results realizations the 1 μA and 24 were performed. achieve a competitive temperature compensation <; 200 ppm/°C wide operating temperatures ° second uses more advanced was also verified...

A front-end ASIC for GEM detectors readout in the CBM experiment is presented. The design has following features: dynamic range of 100 fC, channel hit rate 2 MHz, ENC 1000 e- at 50 pF, power comsumption 10 mW per channel, 6 bit SAR ADC. chip includes 8 analog processing chains, each consisting preamplifier, two shapers (fast and slow), differential comparator an area efficient ADC with 1.2 consunption Msps. also threshold DAC digital part.

In this paper the simple method to reduce switching energy of capacitive digital-to-analog converters (DACs) in low-power successive approximation register (SAR) analog-to-digital (ADCs) is described. The based on well-known monotonic procedure and use one intermediate voltage level during switching. Unlike most recently published methods proposed does not require be accurate. implementation digital control an voltage-level generator considered. To evaluate reduction compared conventional...

In this paper a new switched reference stimulator architecture for the visual cortex stimulation is presented. Compared with present alternatives allows to relax twice requirements of output voltage tolerance and simplify design high (HV) switches. The functionality was proven by fabrication AMS HV 0.35 μm CMOS technology measurement test chip. results show possibility drive currents from -10 mA up 10 into tissue, while electrode-tissue interface resistance 8 kΩ effectively high-voltage...

In this paper a novel high-voltage switch with gate-source overvoltage protection is presented for use in high voltage bidirectional neural interfaces. The proposed can tolerate the difference up to 120V between its terminals. control circuit guarantees operation of HV transistors Safe Operation Area (SOA) by switched follower. be controlled low signals compatible standard CMOS logic levels. simulation performance was carried out AMS 0.35 μm Design Kit.

This paper presents a current driver with novel high voltage (HV) switch schematic for the use as protective recording circuits during stimulation sequence. The can source and sink currents of amplitudes up to ±8.2 mA HV tolerance from 30 V 120 V. mismatch between sourced sinked does not exceed 20 μA. inter pulse is no more than 60 pA. output compliance depends on supply maximum value proposed also tolerates difference 120V its terminals. chip was fabricated AMS 0.35 μm CMOS technology.

This paper describes a design technique for multi-stage high speed precision low-current consumption comparator utilizing charge-storage pre-amplifier. To reduce the average current of preamplifier capacitive dynamic load is used. correct offset voltage pre-amplifier OOS (Output Offset Storage) method Presented verified by 50 MS/s in standard 0.18 μm CMOS process. Achieved power 18 μA, providing input resolution less than 4 mV.

The low power successive approximation register (SAR) analog to digital converter (ADC), which implements the two-step switching, is designed and simulated in 65 nm CMOS of ST Microelectronics. switching allows benefit from more energy-efficient because use three voltage levels without any requirements for stability accuracy third level. Post-layout simulations proposed ADC were performed. It consumes 200 nW at 0.5 V supply 100 kHz sampling rate. effective number bits (ENOB) 9.5 bits, while...

A new method for modeling circuits with switched capacitors (SC) is proposed. Similar to the SPICE-simulation of in their linear mode operation a small ac signals analysis, this allows you determine amplitude and phase frequency responses analog-discrete such as sample-hold SC-filters. The paper shows advantages disadvantages proposed technique compared algorithm used periodic AC analysis simulator RF circuits, SPECTRERF Cadence Design Systems, Bracknell, Berkshire, UK. enables incorporation...

This paper presents a new simple compact current reference topology with first order temperature compensation, which only utilizes 5 CMOS transistors and one resistor. The proposed was used in to design two references 1 μA 24 output functionality proven by measurement the range from -40° C 120°C. chips were produced 0.35 μm technology of AMS. Ten samples characterized. best achieved coefficients -40...120 °C are 143 ppm/°C 166 for 24μA references, respectively. For commercial 0°...85°C 111...

This paper presents an 8-channel neural stimulator application-specific integrated circuit (ASIC) for biphasic stimulation of the visual cortex, fabricated in a 0.35[Formula: see text][Formula: text]m AMS HV process. Each channel is composed standard SPI interface, 8-bit current digital-to-analog converter (DAC) and 120[Formula: text]V compliant output stage. Thus, it possible to deliver tissue arbitrary waveforms with amplitudes up [Formula: text]8.192[Formula: text]mA 32[Formula: text]A...

This paper presents a new compact low supply current reference and simulation-based design procedure to establish the circuit parameters quickly efficiently. To verify proposed procedure, two sub 1 V example circuits for different values (80 nA 800 nA) were designed simulated using 0.35 μm CMOS technology. The are robust against voltage variation without need external bandgap. A line sensitivity of approximately 1-2%/V over range from is achieved in both cases. temperature coefficient (TC)...

A new sampling scheme for successive approximation register (SAR) analog-to-digital converters (ADCs) is proposed in this paper. The switching eliminates two major problems of traditional SAR ADC architectures: first, the high energy demand input driver, because capacitance; and second, trade-off between linearity and, consequently, bottom-plate sampling, area savings upper-plate sampling. allows reduction capacitance to a single unit capacitor use linear without sacrificing double on...

This paper proposes the design of a 6-bit single-ended SAR ADC with variable sampling rate at maximum achievable speed 50 MS/s. The utilizes split capacitor array DAC non-conventional split-capacitor value. influence switches in capacitive on ADC's non-linearity is analysed. According to fulfilled analysis recommendations for and dimensioning are given provide minimum differential (DNL).

This paper describes a pipelined analog-to-digital converter (ADC) employing power and area efficient architecture. The adjacent stages of pipeline share operational amplifiers. In order to keep accuracy the amplifiers in first stages, they use partially sharing technique. feature proposed scheme is that it also shares comparators. capacitors are scaled down along for further reducing chip its consumption. A 9-bit 20-MSamples/s ADC, intended multi-channel mixed-signal chips, has been...

A new energy-efficient architecture for neural spikes acquisition implements pre-detection of before fine conversion. The prediction is based on the low-bit coarse conversion input data with subsequent detection Teager energy operator (TEO). example constructed real neuronal recorded from visual cortex an anesthetized rat shows that systems more efficient as both binary further digitization and full all without pre-detection. proposed system achieves 34% savings compared 10-bit ADC. analog...

A new pipeline SAR ADC architecture without gain between stages is proposed. This can benefit the implementation of high speed ADCs in two ways: first, as a two-stage pipeline, it increases conversion by factor two; second, because capacitive DAC split, avoids switching large capacitors for most significant bits definition. The was verified design 10-bit with maximum 37 MS/s. designed and laid out using 180 nm CMOS technology UMC. simulated ENOB equal to 8.42 bits, power consumption at...