A5070534850- Advancements in Semiconductor Devices and Circuit Design
- Semiconductor materials and devices
- Radio Frequency Integrated Circuit Design
- Electrostatic Discharge in Electronics
- Silicon Carbide Semiconductor Technologies
- Integrated Circuits and Semiconductor Failure Analysis
- Analog and Mixed-Signal Circuit Design
- Electromagnetic Compatibility and Noise Suppression
- Semiconductor Quantum Structures and Devices
- Low-power high-performance VLSI design
- Quantum and electron transport phenomena
- VLSI and Analog Circuit Testing
- Thin-Film Transistor Technologies
- 3D IC and TSV technologies
- Photonic and Optical Devices
- Silicon Nanostructures and Photoluminescence
- Advancements in PLL and VCO Technologies
- Advanced MEMS and NEMS Technologies
- Advanced Power Amplifier Design
- Quantum Dots Synthesis And Properties
- Mechanical and Optical Resonators
- Glass properties and applications
- Superconducting Materials and Applications
- Thermal properties of materials
- Silicon and Solar Cell Technologies
NXP (Netherlands)
2014-2025
Institute of Semiconductors
2019
Taiwan Semiconductor Manufacturing Company (United States)
2008-2011
Philips (Netherlands)
1999-2006
Philips (Finland)
1998-2006
Pennsylvania State University
2006
IMEC
2004-2005
RWTH Aachen University
2005
Utrecht University
1991-1996
This paper describes the latest and most advanced surface-potential-based model jointly developed by The Pennsylvania State University Philips. Specific topics include structure, mobility velocity saturation description, further development verification of symmetric linearization method, recent advances in computational techniques for surface potential, modeling gate tunneling current, inclusion retrograde impurity profile, noise sources. emphasis this is on incorporating MOS device physics...
The RF noise in 0.18-/spl mu/m CMOS technology has been measured and modeled. In contrast to some other groups, we find only a moderate enhancement of the drain current for short-channel MOSFETs. gate on hand is more significantly enhanced, which explained by effects resistance. experimental results are modeled with nonquasi-static model, based channel segmentation, capable predicting both accurately. Experimental evidence shown two additional mechanisms: 1) avalanche associated from bulk 2)...
The impact of scaling on the analog performance MOS devices at RF frequencies was studied. Trends in nominal gate length NMOS from 350-nm to 50-nm CMOS technologies are presented. Both experimental data and circuit simulations with an advanced validated compact model (MOS Model 11) have been used evaluate performance. metrics such as cutoff frequency, maximum oscillation power gain, noise figure, linearity, 1/f were included analysis. focus study drain bias conditions relevant for design. A...
Verilog-A is the de facto standard language that semiconductor industry uses to define compact models. Unfortunately, it easy write models poorly in Verilog-A, and this can lead unphysical model behavior, poor convergence, difficulty understanding maintaining codes. This paper details best practices for writing try help raise quality of modeling throughout industry.
The kinetics of charge transport in quantum point contacts has been studied by low-frequency noise spectroscopy. Temperature and frequency (Lorentzian 1/f) dependences the spectral density are found to vary strongly from device device, but low-T conductance dependence universally exhibits a strong size effect. Based on direct observation time domain spontaneous resistance switching, is identified be due trapping processes which affect local electrostatic potential. A model presented explains...
In this paper, it is shown that self-heating causes a gigantic effect on the capacitances of MOSFETs/FinFETs. The used to determine SOI FinFET thermal impedance and temperature rise during operation.
Extensive measurements of drain current thermal noise are presented for 3 different CMOS technologies and gate lengths ranging from 2 /spl mu/m down to 0.17 mu/m. Using a surface-potential-based compact MOS model with improved descriptions carrier mobility velocity saturation, all the experimental results can be described accurately without invoking heating effects or introducing additional parameters.
The Klaassen-Prins equation is the standard for calculating drain thermal noise of long-channel MOSFETs. We show that not always valid, even present generalizations to include velocity saturation effects short-channel MOSFETs and comprise also induced gate noise.
RF circuit design in deep-submicrometer CMOS technologies relies heavily on accurate modeling of thermal noise. Based Nyquist's law, predictive noise MOSFETs was possible for a long time, provided that parasitic resistances and short-channel effects were properly accounted for. In sub-100-nm technologies, however, microscopic excess starts to play significant role its incorporation models is unavoidable. Here, we will review several crucial ingredients modeling, with emphasis technologies....
We present a MOS Capacitance-Voltage measurement methodology that, contrary to methods, is highly robust against gate leakage current densities up 1000 A/cm/sup 2/. The features specially designed RF test structures and frequencies. It allows parameter extraction in the full range of accumulation, depletion, inversion.
A new noise-figure measurement method, which combines the simplicity of "classical" Y-factor method with accuracy widely used "cold noise-source" is reported. Implemented in our fully automated wide-band 1-18-GHz on-wafer noise-parameter system, accurate results are obtained using a small set precharacterized source impedances. We illustrate and its data taken on low-noise GaAs pseudomorphic high electron-mobility transistor device, quantify impact instrumental uncertainties extracted noise...
In this paper, we develop a statistical model for random telegraph noise (RTN) related low-frequency (LFN). With our proposed model, one can calculate the expected value and variability of as function bias device parameters. We clarify why RTN/LFN does not follow 1/ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\surd $ </tex-math></inline-formula> area dependence. The explains effect halo implanted...
A large-signal non-quasi-static (NQS) model for RF CMOS circuit simulation is presented that can be built from channel segments described by conventional QS models like BSIM3 or MOS Model 9. This NQS shown to give a very accurate prediction of the high-frequency behaviour intrinsic transconductance, power gain and input resistance.
In this paper, we develop a method to derive degradation formulas for time-varying stress from the constant-bias case, discuss its limitations, and apply it set of radio-frequency (RF) experiments. First, will give new derivation well-known power-law case without invoking any specific physical model. Next, show that can be generalized broader class functions type <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g</i> (...
In this paper a new physical gate leakage model is introduced, which both accurate and simple. It only uses 5 parameters, making parameter extraction straightforward. As result the can be used to extract effective length for modern CMOS technologies. The influence of current on RF performance studied.
The surface-potential-based compact MOS model PSP is reviewed with special emphasis to features of interest analog and RF designers. Various aspects the are discussed, such as Gummel symmetry, capacitance reciprocity at <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:xlink="http://www.w3.org/1999/xlink">DS</sub> = 0 V, parasitic resistances, junction modeling, distortion noise modeling. Examples from circuit design used illustrate...
This paper presents the results of several qualitative ldquobenchmarkrdquo tests that were used to verify physical behavior PSP model and its usefulness for future generations CMOS IC design. These include newly developed new experimental data stemming from low-power, RF, mixed-signal, analog applications MOSFETs.
We have optimized 3 key RF devices realized in standard logic 90 nm CMOS technology and report a record performance terms of n-MOS maximum oscillation frequency f/sub max/ (280 GHz), varactor tuning range inductor quality factor.
A new physics-based junction model for CMOS, called JUNCAP2, is presented. It contains single-piece formulations the Shockley-Read-Hall generation/recombination current and trap-assisted tunneling (TAT) current, which are valid both in forward reverse mode of operation. Moreover, TAT extends existing (IEEE Trans. Electron Devices, vol. 39, p. 2090, 1992) to high electric fields encountered today's CMOS technologies. Furthermore, expressions capacitance, ideal band-to-band avalanche...
In compact transistor modeling for circuit simulation, the capacitances of conventional MOS devices are commonly determined as derivatives terminal charges, which in their turn obtained from so-called Ward-Dutton charge partitioning scheme. For with a laterally nonuniform channel doping profile, however, it is shown this paper that no charges exist can be derived. Instead, such devices, new model presented themselves. Furthermore, method given to incorporate capacitance into simulators,...
Low Frequency Noise (LFN) and Random Telegraph (RTN) are performance limiters in many analog digital circuits. For small area devices the noise PSD can easily vary by more than 4 orders of magnitude, imposing serious threat circuit possibly reliability. In this paper we propose a new RTN/LFN variability scaling model. The model is validated through numerous experimental results for n-channel p-channel from different CMOS nodes. Using demonstrate that found our measurements be explained using...
The influence of the gate-oxide thickness, substrate dope, and gate bias on input-referred spectral 1/f noise density Sv/sub gate/ has been experimentally investigated. It is shown that dependence oxide thickness can be described by model Hung, predicted for future technologies. Discrepancies with ITRS roadmap are discussed.