A5009412835- Radio Frequency Integrated Circuit Design
- Advancements in PLL and VCO Technologies
- Advancements in Semiconductor Devices and Circuit Design
- Electromagnetic Compatibility and Noise Suppression
- Microwave Engineering and Waveguides
- Analog and Mixed-Signal Circuit Design
- Semiconductor materials and devices
- Advanced Wireless Communication Techniques
- Semiconductor Lasers and Optical Devices
National Institute of Technology Sikkim
2020-2023
Journal of Circuits, Systems and ComputersAccepted Papers No AccessDesign CML Based Odd Frequency Divider using Delay cell for Low-Power ApplicationLokenath Kundu, Subhanil Maity, Sourav Nath, Gaurv Singh Baghel, K.L. BaishnabLokenath Maity Search more papers by this author , Nath Baghel Baishnab https://doi.org/10.1142/S0218126625501865Cited by:0 (Source: Crossref) PreviousNext AboutFiguresReferencesRelatedDetailsPDF/EPUB ToolsAdd to favoritesDownload CitationsTrack CitationsRecommend...
A power-efficient high speed MOS current mode logic (MCML)-based divide-by-5 pre-scaler is proposed in this paper. Optimized latches and XOR gates are used order to design the pre-scaler. The realized 180 nm CMOS process technology simulation results show that can faithfully work up an operating frequency of 12.12 GHz worst case corner with excellent power head performance. maximum dissipation core circuit 1.39 mW under 1.8 V supply. performance corresponds figure merit: FoM 9.4 dB which...
Abstract This paper presents power and area optimized, high‐speed metal‐oxide‐semiconductor (MOS) current mode logic (MCML)‐based frequency dividers. Each differential pair in the divider is sized separately to minimize overall consumption. The divide‐by‐2 has been realized a 180‐nm complementary MOS (CMOS) process technology, postlayout simulation results show that proposed can work up an operating of 18.8 GHz worst‐case corner with maximum dissipation 1.715 mW under 1.8‐V supply. It gives...
Current-mode logic (CML) pre-scalers are extensively used in radio-frequency transceivers and phase-locked loops for its wide division range. This paper presents a methodology the design of metal-oxide-semiconductor CML (MCML) pre-scaler compliant with ZigBee standard. A hand calculation based general analysis is presented this work. delay element has been introduced architecture theoretical foundations method have explained. The applied to divide-by-3 pre-scaler.