Eric Schneider

ORCID: 0000-0003-2296-1956
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About
Contact & Profiles
Research Areas
  • VLSI and Analog Circuit Testing
  • Radiation Effects in Electronics
  • Integrated Circuits and Semiconductor Failure Analysis
  • Low-power high-performance VLSI design
  • Lubricants and Their Additives
  • Embedded Systems Design Techniques
  • Fuel Cells and Related Materials
  • Nuclear Physics and Applications
  • VLSI and FPGA Design Techniques
  • Physical Unclonable Functions (PUFs) and Hardware Security
  • Tribology and Wear Analysis
  • Chemical Reactions and Isotopes
  • Cold Fusion and Nuclear Reactions
  • Semiconductor materials and devices
  • Membrane-based Ion Separation Techniques
  • Radioactive contamination and transfer
  • Electrochemical Analysis and Applications
  • Parallel Computing and Optimization Techniques
  • Advanced Battery Materials and Technologies
  • Metal Alloys Wear and Properties
  • Nuclear Materials and Properties
  • Advanced machining processes and optimization
  • Nanofluid Flow and Heat Transfer
  • Power Transformer Diagnostics and Insulation
  • Analytical Chemistry and Sensors

University of Stuttgart
2012-2020

The University of Texas at Austin
2015-2016

General Motors (United States)
1992-2013

Materials Systems (United States)
2011

ParisTech
2010

École nationale supérieure d'arts et métiers
2010

General Motors (Poland)
2007-2009

The solid electrolyte interphase (SEI) forms during the initial cycles in lithium ion batteries and evolves throughout battery life. By protecting electrode passing ions, SEI plays an important role performance degradation of batteries. Identifying how cycling helps us understand mitigate degradation. In this work, we address chemical electrochemical evolution its formation process provide a correlation between these properties. It is found that chemistry, not just thickness, has distinct...

10.1021/jp4111019 article EN The Journal of Physical Chemistry C 2013-12-19

Runtime reconfigurable architectures based on Field-Programmable Gate Arrays (FPGAs) are attractive for realizing complex applications. However, being manufactured in latest semiconductor process technologies, FPGAs increasingly prone to aging effects, which reduce the reliability of such systems and must be tackled by mitigation application fault tolerance techniques. This paper presents module diversification, a novel design method that creates different configurations runtime modules. Our...

10.1109/test.2013.6651926 article EN 2013-09-01

The equilibrium and transport properties of a poly(perfluorosulfonic acid) membrane containing dilute sulfuric acid solution are investigated over the temperature range from 20 to 90°C, which is interest for polymer‐electrolyte fuel cells. porosity, proton diffusion coefficient, electrokinetic permeability measured tabulated as function temperature. A combination electrochemical radiotracer techniques employed. Péclet number, dimensionless group that characterizes importance electro‐osmotic...

10.1149/1.2069094 article EN Journal of The Electrochemical Society 1992-12-01

Runtime reconfigurable architectures based on Field-Programmable Gate Arrays (FPGAs) allow areaand power-efficient acceleration of complex applications. However, being manufactured in latest semiconductor process technologies, FPGAs are increasingly prone to aging effects, which reduce the reliability and lifetime such systems. Aging mitigation fault tolerance techniques for fabric become essential realize dependable architectures. This article presents an accelerator diversification method...

10.1109/tc.2016.2616405 article EN IEEE Transactions on Computers 2016-10-11

In lubricated sliding contacts, components wear out and the lubricating oil ages with time. The present work explores interactive influence between lubricant aging component wear. flat face of a steel pin is slid against rotating disk under near isothermal conditions while contact immersed in reservoir (hexadecane). chemical changes time are measured by vibrational spectroscopy gas chromatography. corresponding chemistry surface recorded using X-ray photoelectron morphology worn pins;...

10.1021/am200375a article EN ACS Applied Materials & Interfaces 2011-06-18

Field-programmable gate array (FPGA)-based reconfigurable systems allow the online adaptation to dynamically changing runtime requirements. The reliability of FPGAs, being manufactured in latest technologies, is threatened by soft errors, as well aging effects and latent defects. To ensure reliable reconfiguration, it mandatory guarantee correct operation fabric. This can be achieved periodic or on-demand testing. paper presents a system architecture for runtime-reconfigurable systems, which...

10.1109/tc.2013.53 article EN IEEE Transactions on Computers 2013-06-28

Delay fault simulation is an essential task during test pattern generation and reliability assessment of electronic circuits. With the high sensitivity current nano-scale designs toward even smallest delay deviations, small gate faults has become extremely important. Since these have a subtle impact on timing behavior, traditional approaches based abstract models are not sufficient. Furthermore, detection compromised by ubiquitous variations in manufacturing processes, which causes actual...

10.1109/tcad.2016.2598560 article EN IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 2016-08-30

The thermal conductivity of boron nitride/ethylene glycol (BN/EG) nanofluids was investigated by transient hot-wire method and two abnormal phenomena reported. One is the higher enhancement for BN/EG at very low-volume fraction particles, other synthesized with large BN nanoparticles (140 nm) which than that small (70 nm). chain-like loose aggregation responsible increment low particles volume fraction. And difference in specific surface area aspect ratio may be main reasons between...

10.1186/1556-276x-6-443 article EN cc-by Nanoscale Research Letters 2011-07-09

Aging effects in nano-scale CMOS circuits impair the reliability and Mean Time to Failure (MTTF) of embedded systems. Especially for FPGAs that are manufactured latest technology node, aging is amajor concern. We introduce first cross-layer aging-aware placement method accelerators FPGA-based runtime reconfigurable architectures. It optimizes stress distribution by accelerator at runtime, i.e. which region an shall be reconfigured. Additionally, it logic synthesis time diversify resource...

10.1109/iccad.2015.7372547 article EN 2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) 2015-11-01

Abstract One of the major obstacles to overcome for realization economical hydrogen‐oxygen, polymer‐electrolyte fuel cells is high capital cost inert perfluorosulfonic acid (PSA) membranes, which provide a pathway ionic transport between cell electrodes. It has recently been shown that composite polymer membranes can be synthesized by depositing PSA polymers onto porous poly(tetrafluoroethyene) (PTFE) substrates. The resulting are mechanically durable and quite thin relative traditional...

10.1002/aic.690380110 article EN AIChE Journal 1992-01-01

The precise estimation of dynamic power consumption, droop and temperature development during scan test require a very large number time-aware gate-level logic simulations. Until now, such characterizations have been feasible only for rather small designs or with reduced precision due to the high computational demands. We propose new, throughput-optimized timing simulator on running GPGPUs accelerate these tasks by more than two orders magnitude thus providing first time comprehensive toggle...

10.1109/ats.2012.23 article EN 2012-11-01

An industrial base oil, a blend of different paraffin fractions, is heated to 130 °C (1) in the ambient and (2) for use as lubricant steel pin on disk sliding experiment. The oil was tested with without test antioxidants: dimethyl disulfide (DMDS) alkylated diphenylamine (ADPA). Primary secondary oxidation products were monitored continuously by FTIR over 100 h period. In addition, friction wear same period chemical transformation surface XPS. objective this work observe catalytic action...

10.1021/jp309824r article EN The Journal of Physical Chemistry C 2013-01-04

In technologies affected by variability, the detection status of a small-delay fault may vary among manufactured circuit instances. The same be detected, missed or provably undetectable in different We introduce first complete flow to accurately evaluate and systematically maximize test quality under variability. As number possible instances is infinite, we employ statistical analysis obtain set that achieves fault-efficiency target with an user-defined confidence level. algorithm combines...

10.1109/ets.2014.6847806 article EN 2014-05-01

The simulation of delay faults is an essential task in design validation and reliability assessment circuits. Due to the high sensitivity current nano-scale designs against smallest deviations, small recently became focus test research. Because subtle impact, traditional fault approaches based on abstract timing models are not sufficient for representing faults. Hence, accurate have be utilized, which quickly become inapplicable larger due computational requirements. In this work we present...

10.5555/2755753.2757084 article EN Design, Automation, and Test in Europe 2015-03-09

Aging effects in nano-scale CMOS circuits impair the reliability and Mean Time to Failure (MTTF) of embedded systems. Especially for FPGAs that are manufactured latest technology node, aging is a major concern.We introduce first cross-layer aging-aware placement method accelerators FPGA-based runtime reconfigurable architectures. It optimizes stress distribution by accelerator at runtime, i.e. which region an shall be reconfigured. Additionally, it logic synthesis time diversify resource...

10.5555/2840819.2840825 article EN International Conference on Computer Aided Design 2015-11-02

Small gate delay faults (SDFs) are not detectable at-speed, if they can only be propagated along short paths. These hidden (HDFs) do influence the circuit's behavior initially, but may indicate design marginalities leading to early-life failures, and therefore cannot neglected. HDFs detected by faster-than-at-speed test (FAST), where typically several different frequencies used maximize coverage. A given set of patterns P potentially detects a HDF it contains pattern sensitizing path through...

10.1109/ats.2015.26 article EN 2015-11-01

The simulation of delay faults is an essential task in design validation and reliability assessment circuits. Due to the high sensitivity current nano-scale designs against smallest deviations, small recently became focus test research. Because subtle impact, traditional fault approaches based on abstract timing models are not sufficient for representing faults. Hence, accurate have be utilized, which quickly become inapplicable larger due computational requirements. In this work we present...

10.7873/date.2015.0077 article EN Design, Automation & Test in Europe Conference & Exhibition (DATE), 2015 2015-01-01

The radiotracer technique of surface layer activation was used to study piston ring wear rates in the Detroit Diesel Allison «Series 60» engine. Radioactive Mn induced chromium face by bombardment with an α beam from a particle accelerator. Wear determined measuring accumulation radioactive debris oil during engine operation and radiation intensity rings outside between intervals

10.4271/880672 article EN SAE technical papers on CD-ROM/SAE technical paper series 1988-02-01

Marginal hardware introduces severe reliability threats throughout the life cycle of a system. Although marginalities may not affect functionality circuit immediately after manufacturing, they can degrade into hard failures and must be screened out during manufacturing test to prevent early failures. Furthermore, their evolution in field proactively monitored by periodic tests before actual occur. In recent years, small delay faults (SDFs) have gained increasing attention as possible...

10.1109/tcad.2018.2864255 article EN IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 2018-08-07

Aging monitors can indicate the wear-out phase of a semi-conductor device before it will actually fail, and allow use integrated circuits in applications with high safety reliability demands. In early lifecycle systems, small delay faults may problems life failures, even if they are smaller than slack any path neither alter functional behavior system nor violate aging guardband. One option to detect this type hidden (HDFs) is application faster-than-at-speed-test (FAST). This paper shows...

10.1109/ats.2018.00028 article EN 2018-10-01
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