A5031742777- Quantum Computing Algorithms and Architecture
- Quantum Information and Cryptography
- Quantum and electron transport phenomena
- Neuroscience and Neural Engineering
- Physical Unclonable Functions (PUFs) and Hardware Security
- Integrated Circuits and Semiconductor Failure Analysis
Riverlane (United Kingdom)
2024
Lancaster University
2021
Quantum error correction enables the preservation of logical qubits with a lower rate than physical rate, performance depending on decoding method. Traditional approaches rely binarization (“hardening”) readout data, thereby ignoring valuable information embedded in analog (“soft”) signal. We present experimental results showcasing advantages incorporating soft into process distance-3 (<a:math xmlns:a="http://www.w3.org/1998/Math/MathML" display="inline"...
Abstract Quantum dot physically unclonable functions (QD-PUFs) provide a promising solution to the issue of counterfeiting. When quantum dots are deposited on surface create token, they form unique pattern that is unlikely ever be reproduced in another token manufactured using same process. It would also an extreme engineering challenge deterministically place forgery specific device. The degradation optical response over time, however, places limitation their practical usefulness. Here we...
Quantum error correction enables the preservation of logical qubits with a lower rate than physical rate, performance depending on decoding method. Traditional approaches, relying binarization (`hardening') readout data, often ignore valuable information embedded in analog (`soft') signal. We present experimental results showcasing advantages incorporating soft into process distance-three ($d=3$) bit-flip surface code transmons. To this end, we use $3\times3$ data-qubit array to encode each...
Quantum error correction (QEC) will be essential to achieve the accuracy needed for quantum computers realise their full potential. The field has seen promising progress with demonstrations of early QEC and real-time decoded experiments. As advance towards demonstrating a universal fault-tolerant logical gate set, implementing scalable low-latency decoding crucial prevent backlog problem, avoiding an exponential slowdown maintaining fast clock rate. Here, we demonstrate feedback FPGA decoder...