Zongyuan Li

ORCID: 0000-0003-3567-6978
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About
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Research Areas
  • Analog and Mixed-Signal Circuit Design
  • Quantum and electron transport phenomena
  • Advancements in Semiconductor Devices and Circuit Design
  • Quantum Computing Algorithms and Architecture
  • Neural Networks and Reservoir Computing
  • Neural Networks and Applications
  • Integrated Circuits and Semiconductor Failure Analysis
  • VLSI and Analog Circuit Testing
  • Machine Fault Diagnosis Techniques
  • Quantum Information and Cryptography
  • Smart Grid and Power Systems
  • Optical Network Technologies
  • Advanced Photonic Communication Systems
  • Semiconductor materials and devices
  • Engineering Diagnostics and Reliability
  • Radio Frequency Integrated Circuit Design
  • Energy Load and Power Forecasting
  • Topic Modeling
  • Power Systems and Technologies
  • Advanced Memory and Neural Computing
  • Sensor Technology and Measurement Systems
  • Text and Document Classification Technologies
  • Sentiment Analysis and Opinion Mining
  • Electrostatic Discharge in Electronics
  • Fault Detection and Control Systems

Yokohama National University
2022-2024

Hohai University
2023

KU Leuven
2023

Wuhan University
2021

Abstract We believe that the Adiabatic Quantum-Flux-Parametron (AQFP) circuit, as a new type of low-power superconducting can be applied in various fields, such using its high precision to determine phase input signals. To improve AQFP, it is necessary reduce gray zone circuit. In this paper, we investigate digital integration method AQFP circuit system and enhance precision. Theoretical results show becomes narrower increases more data points are integrated.
Additionally, establish...

10.1088/1361-6668/adabcb article EN Superconductor Science and Technology 2025-01-19

For the binary neural network (BNN), We design a max pooling operation circuit (MPOC) using single-flux-quantum circuits based on multiple data comparators. To continuously compare and find maximum value, comparator uses internal state of non-destructive read-out (NDRO) flip-flop NDRO with complementary outputs to store value. The MPOC is designed gate-level pipeline architecture avoiding use feedback loops or tree structures when comparing data. Therefore, area reduced by approximately 74%...

10.1109/tasc.2023.3241144 article EN IEEE Transactions on Applied Superconductivity 2023-01-31

Abstract In this study, the on‐chip generation of microwave signals are proposed for controlling nearby quantum bits in a low‐temperature environment, utilizing superconducting logical and RF components. To achieve enhanced amplitude microwave, single flux (SFQ) pulse pairs employed, which can have either same or reversal polarity, serving as basic elements generator. The SFQ then combined wave‐shaped by using combining filter, finally outputs desired with narrow line‐width. signal...

10.1002/qute.202400001 article EN Advanced Quantum Technologies 2024-04-11

We propose an asynchronous single flux quantum (SFQ) logic gate composed of a conventional clocked and input signal merger that generates self-clock for the gate. By using this self-clocking, we can design any 0-preserving gate, including exclusive OR (XOR). The proposed SFQ gates have adjustable allowable skew by varying delay between internal clock evaluate AND, OR, XOR approximately 8 ps assuming use 10 kA/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML"...

10.1109/tasc.2023.3244148 article EN IEEE Transactions on Applied Superconductivity 2023-02-10

This paper describes a conditon monitoring systems for helicopter main gearbox using wavelet packet transform (WPT) and neural network (WNN). According to the fault characteristics of gearbox, diagnosis method that combining WPT WNN with threshold is proposed. First noise removed from vibration signals, then denoising signals are decomposed by WPT, extract standard deviation coefficients each level as input WNN, learning rates momentum factors used adjust network, batch training applied it...

10.1109/icqr2mse.2011.5976651 article EN International Conference on Quality, Reliability, Risk, Maintenance, and Safety Engineering 2011-06-01

We design a binary convolution operation circuit (BCOC) using single-flux-quantum for high-speed and energy-efficient neural network. The proposed is used operations kernel size of 3 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$ \times $</tex-math></inline-formula> 3, which accelerates the forward propagation process network (BNN). analyze propose bisection method optimization. BCOC designed with...

10.1109/tasc.2022.3140286 article EN IEEE Transactions on Applied Superconductivity 2022-01-04

Abstract With the increasing processor performance requirements of convolutional neural networks, we believe that research on superconducting networks based single flux quantum (SFQ) circuits holds significant potential. However, typical multiply and accumulate operations used in often lead to a increase circuit area due limitations integration density current SFQ fabrication process. In this work, propose binary processing element (PE) utilizes time-domain signal expression. Time-domain...

10.1088/1361-6668/ad2fd9 article EN Superconductor Science and Technology 2024-03-04

Abstract Superconducting neural networks hold significant potential for future applications such as natural language processing and image recognition. To this end, we propose a binary computing unit implemented using hybrid circuit of cryogenic CMOS superconducting technologies. It offers two main advantages: firstly, utilize current-mode computations weight calculations, significantly reducing the unit’s footprint enabling higher integration in future. Secondly, all are performed...

10.1088/1361-6668/ad44e2 article EN Superconductor Science and Technology 2024-04-29

Because the increasingly promoted high proportion of power electronics based load devices and distributed sources, impact on short circuit currents caused by clustered loads when fault occurred cannot be ignored. It is great value to establish a correct accurate model for purpose simulation in cases, exiting founded only suitable small disturbance cases. So an AI parameter identification algorithm proposed. Firstly, according sensitivity analysis, parameters which have significant result are...

10.1109/icpst56889.2023.10165450 article EN 2023-05-05

The study aims to investigate the method of improving data retention for logic flash by studying different process condition and analyzing how much current drops after 250C baking times in details. According experimental results, it is shown that not only material thickness HTO gate oxide capacitor, but also thermal wet chemical have influence flash.

10.1109/isne56211.2023.10221579 article EN 2023-05-12

This paper proposes a 10 GHz quadruple-tail comparator with double feedforward paths, making it less input-dependent and suitable for high-speed synchronous SARs. The prototype in 28 nm CMOS achieves 26.4 ps delay at 1 mV input -5.8ps/decade slope. It the shortest smallest slope of any recently published comparator. Furthermore, proposed work has flat noise across common mode from 0.4 V to 0.8 V.

10.1109/esscirc59616.2023.10268823 article EN ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC) 2023-09-11

Semantic features, word sequences, and syntactic structures are three key elements for human classification of multi-category sentiment texts. However, current neural network models focus mostly on semantic features thereby losing structure information in modeling limiting accuracy. In this paper, we combine at different levels propose an enhanced model with dual-granularity syntax-path encoding classification. particular, the level, utilized two long short-term memories to process units...

10.1109/ijcnn52387.2021.9533770 article EN 2022 International Joint Conference on Neural Networks (IJCNN) 2021-07-18
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