An RF-DC power conversion system is designed to efficiently convert far-field RF energy DC voltages at very low received and voltages. Passive rectifier circuits are in a 0.25 mum CMOS technology using floating gate transistors as rectifying diodes. The 36-stage can rectify input 50 mV with voltage gain of 6.4 operates 5.5 muW(22.6 dBm). Optimized for far field, the circuit distance 44 m from 4 W EIRP source. high range achieved load current make it ideal use passively powered sensor networks.

A dynamic element matching algorithm, data weighted averaging, is introduced for use in multibit /spl Delta//spl Sigma/ converters. Using this distortion spectra from DAC linearity errors are shaped by first-order noise shaping, resulting a range improvement of 9 dB/octave when dominate. Combining technique with random dithering nearly eliminates the aliasing into baseband. Simulations show that only 1% 110 dB signal-to-noise ratio (18 b) achieved third-order 3-b modulator an oversampling 128.

New power conversion circuits to interface a piezoelectric micro-power generator have been fabricated and tested. Circuit designs measurement results are presented for half-wave synchronous rectifier with voltage doubler, full-wave passive circuit connected the generator. The measured efficiency of doubler in 0.35-/spl mu/m CMOS process is 88% output exceeds 2.5 /spl mu/W 100-k/spl Omega/, 100-nF load. two rectifiers (passive synchronous) were 0.25-/spl process. peak 66% 220-k/spl Omega/...

Switched-current (SI) circuits represent a current-mode analog sampled-data signal processing technique realizable in standard digital CMOS technologies. Unlike switched-capacitor (SC) circuits, SI require only process. use MOS transistors as the storage elements to provide memory capability. Similar operation of dynamic logic voltage is sampled onto gate MOSFET and held on its noncritical capacitance. The causes corresponding current drain, usually proportional square gate-to-source...

This paper describes the first 32 kHz low-power MEMS-based oscillator in production. The primary goal is to provide a small form-factor (1.5 × 0.8 mm 2 ) for use as crystal replacement space-constrained mobile devices. generates an output frequency of 32.768 and its binary divisors down 1 Hz. stability over industrial temperature range (-40 °C 85 °C) ±100 ppm (XO) or ±3 with optional calibration compensated (TCXO). Supply currents are 0.9 μA XO 1.0 TCXO at supply voltages from 1.4 V 4.5 V....

This paper describes a design-oriented scalable macromodel for substrate noise coupling in heavily-doped substrates. The model requires only four parameters which can be readily extracted from small number of device simulations or measurements. Once these have been determined, the used design any spacing between injection and sensing contacts different contact geometries. scalability with separation width provides insight into optimization issues prior to during layout phase. is validated...

The design and implementation of switched-current (SI) ladder filters is described. basic current-mode circuits, including the SI differential integrator/summer are developed. shown to be directly analogous switched-capacitor (SC) integrator/summer; thus, all synthesis techniques developed for SC can used synthesize filters. Signal flowgraph presented. nonideal characteristics that limit their accuracy evaluated. Clock-feedthrough device mismatch induced errors more severe in present circuit...

A model for /spl Delta//spl Sigma/ A/D modulators that allows stability analysis using linear methods is described. This draws out the dependence of on system parameters such as integrator gains and delays well dynamic characteristics input amplitude, transients, initial conditions. In addition, high-order systems are found to be prone a previously unrecognized source instability, saturation limit cycles. Stabilizing requires controlling cycles, minimizing delays, proper choice gains. The...

A continuous-time delta-sigma A/D modulator with 5 MS/s output rate in a 2.5 V 0.25 mum CMOS process is presented. The has fifth-order single-stage, dual-loop architecture allowing nearly one clock period quantizer delay. multi-bit used to increase resolution and non-return-to-zero DACs are adopted reduce jitter sensitivity. Capacitor tuning utilized overcome loop coefficient shifts due variations. Self-calibration implemented suppress current-steering DAC mismatch. Clocked at 60 MHz, the...

In this paper, a component efficient multiple-input boost converter is proposed to extract power from multiple low-power energy harvesting sources. The time-multiplexed operation of the enables sharing stage between different input sources, leading reduced count. Combined with novel digital control method and universal tracking algorithm, maximum automatically extracted for all A dual-input prototype built off-the-shelf components validates overall strategy commercially available...

Low power devices promote the development of micropower generators (MPGs). This paper presents a novel conditioning circuit (PCC) that enables maximum extraction from piezoelectric MPG. Synchronous rectification (SR) is employed to improve PCC efficiency. A simplified model generator developed for simulation. Performance proposed verified by PSpice simulation and experimental results. output 18.8 /spl mu/W has been extracted single Arbitrary waveform representation (AWGR) flexing membrane...

A new dynamic element matching (DEM) algorithm, referred to as data weighted averaging (DWA), is presented for improving DAC linearity in multi-bit delta-sigma (/spl Delta//spl Sigma/) converters. It out-performs all previously described algorithms. By cycling through the elements of at a rate dependent on input DAC, are exercised maximum possible. With this distortion spectra shaped by first-order noise shaping which results 9 dB/octave improvement converter range when errors dominate...

An ultralow-power super-regenerative receiver for BFSK modulated signals has been designed and fabricated in a standard 0.18-μm CMOS process. The use of modulation allows the to operate at higher data rates also gives an approximate 3-dB SNR performance increase over more traditional OOK modulation. A fast calibration scheme absence external inductor make it ideal sensor networks. power consumption 215 μW from 0.65-V supply area 0.55 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML"...

A fully integrated CMOS GPS receiver RF front-end is presented. Systematic circuit optimizations for ultra-low voltage operation including subthreshold biasing, a novel mixer-VCO interface, and charge neutralization enable the supply to be dramatically reduced as means save power. The 250 mV lowest ever reported any date. Its 352 μW power consumption represents three times savings compared prior front-ends in literature. prototype was fabricated 1P8M 130 nm process includes variable gain...

A fully balanced current-mode circuit topology has been developed for analog signal processing applications. The basic building block, a 5-V current mirror/amplifier, fabricated using standard 2- mu m n-well CMOS process. With peak to bias ratio i/I=0.5, the open-loop total harmonic distortion was-70 dB. addition of sampling switches, mirror/amplifier forms switched-current integrator that exhibits first-order cancellation clock-feedthrough/charge-injection effects. Fully SI ladder filters...

A technique to reduce in-band tones in switch-mode power supplies is described. It takes advantage of the noise-shaping properties delta-sigma (/spl Delta//spl Sigma/) modulator eliminate spikes normally present switching supplies. framework introduced for comparing conventional pulsewidth modulated (PWM) controller and this approach. buck converter test circuit constructed that designed a PWM clocked at 200 kHz then substituted with /spl Sigma/ 400 kHz. The RMS noise 14.9 mW compared rms...

A new dynamic element matching (DEM) algorithm, referred to as rotated data weighted averaging (RDWA), is implemented in a third-order /spl Sigma//spl Delta/ digital-to-analog converter (DAC) with 64/spl times/ oversampling and conversion bandwidth of 25 kHz. The systematic random errors are considered the design 14-bit converter. DAC fabricated 2-/spl mu/m CMOS process includes on-chip reconstruction filter. prototype was designed test performance without DEM, (DWA), RDWA. results show that...

A new enhanced swing differential Colpitts VCO architecture enables oscillations to go beyond both the supply voltage and ground making it suitable for low operation. Analysis oscillation frequency, differential- common-mode oscillations, amplitude of oscillation, start-up condition provides insight into oscillator operation design considerations. Operating at 4.9 GHz, consumes from 1.9 mW 3 voltages 400 mV 500 mV, respectively. The 130 nm CMOS VCO's measured phase noise ranges <formula...

A novel low power compact loop filter using a single amplifier biquad (SAB) network is presented for continuous-time (CT) delta-sigma (ΔΣ) modulators. This new technique reduces consumption and die area by minimizing the number of active elements simplifying modulator topology. The SAB has transfer function (TF) zero, which implements local feedforward (FF) path in system-level diagram. By having FF branch embedded network, branches to summing block based topology reduced half conventional...

This paper presents a new stage-sharing technique in discrete-time (DT) 2-2 MASH delta-sigma (ΔΣ) ADC to reduce the modulator power consumption and chip die area. The proposed shares all active blocks between two stages of modulator. utilizes second-order Chain Integrators with Weighted Feed-forward Summation (CIFF) Cascade Distributed Feedback Branches (CIFB) architectures for first second stages, respectively. Using technique, integrator adder op-amps stage are shared stage. In addition...

Distortion due to device mismatches and clock-feedthrough in switched-current circuits is analyzed. A replication-based current feedthrough cancellation technique that reduces the more than 20 dB proposed. SPICE simulation results for this circuit are given.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A CMOS transconductor uses resistors at the input and an OTA in unity-gain feedback to achieve 80-dB spurious-free dynamic range (SFDR) for 3.6-V/sub pp/ differential inputs up 10 MHz. The combination of negative around operational transconductance amplifier (OTA) allows this accommodate a swing 4 V with 3.3-V supply. total harmonic distortion (THD) is -77 dB MHz third-order intermodulation spurs measure less than -79 dBe 1.8-V/sub 1 core dissipates 10.56 mW from supply occupies 0.4 mm/sup...

Delta-sigma (/spl Delta//spl Sigma/) analog-to-digital converters (ADC's) rely on oversampling to achieve high-resolution. By applying multibit quantization overcome stability limitations, a circuit topology with greatly reduced requirements is developed. A 14-bit 500-kHz /spl Sigma/ ADC described that uses an ratio of only 16. fourth-order embedded modulator, four-bit quantizer, and self-calibrated digital-to-analog converter (DAC) are used this performance. Although the high-order...

The most pressing and critical needs for engineering graduates in 2013 beyond are to be natural innovators who able integrate their knowledge solve complex problems. This paper introduces an integrated platform learning/spl trade/ as a solution meet these needs. learning provides environment innovation, while integrating curriculum into coherent whole.