A5008165880- Analog and Mixed-Signal Circuit Design
- Advancements in PLL and VCO Technologies
- Advancements in Semiconductor Devices and Circuit Design
- Low-power high-performance VLSI design
- Semiconductor Lasers and Optical Devices
- Photonic and Optical Devices
- CCD and CMOS Imaging Sensors
- Sensor Technology and Measurement Systems
- Radio Frequency Integrated Circuit Design
- Advanced MEMS and NEMS Technologies
- Optical Network Technologies
- Advanced Adaptive Filtering Techniques
- Digital Filter Design and Implementation
- Advanced Photonic Communication Systems
- Advanced Power Amplifier Design
- Semiconductor Quantum Structures and Devices
- Mechanical and Optical Resonators
- Acoustic Wave Resonator Technologies
- Numerical Methods and Algorithms
- Image Processing Techniques and Applications
- Innovative Energy Harvesting Technologies
- Advanced DC-DC Converters
- Neuroscience and Neural Engineering
- Higher Education Learning Practices
- VLSI and FPGA Design Techniques
Laboratoire de Génie Électrique et Électronique de Paris
2015-2023
Centre National de la Recherche Scientifique
2015-2023
Université Paris-Saclay
2016-2021
CentraleSupélec
2015-2021
Sorbonne Université
2016-2021
Université Paris-Sud
2019
Supélec
2006-2015
École Normale Supérieure - PSL
1993-2011
Laboratoire de Mesure du Carbone 14
2008
Heriot-Watt University
1998-1999
Today's applications such as broadband satellite receivers, cable TVs, and software-defined radios require highly efficient ADCs with high sampling rates resolutions. A time-interleaved ADC (TIADC) is a popular architecture used to achieve this goal. However, structure suffers from mismatches between the sub-converters, which cause errors on output signal, more significantly, decrease SFDR. These can be severe limitation in reception, where both narrowband wideband signals are used. This...
A methodology for analysis and synthesis of lowpass sigma-delta (/spl Sigma//spl Delta/) converters is presented in this paper. This method permits to synthesize /spl Delta/ modulators employing continuous-time filters from discrete-time topologies. The based on the discretization model using a discrete simulator which more efficient than an analog simulator. Finally, realistic design second-order modulator with compensation non ideal behavior DAC given. Moreover, simulation results show...
A methodology for analysis and synthesis of lowpass sigma-delta (/spl Sigma//spl Delta/) converters is presented in this paper. This method permits to synthesize /spl Delta/ modulators employing continuous-time filters from discrete-time topologies. The based on the discretization model using a discrete simulator which more efficient than an analog simulator. Finally, realistic design second-order modulator with compensation non ideal behavior DAC given. Moreover, simulation results show...
The High-Speed Optoelectronic Memory Systems (HOLMS) project, sponsored by the European Union Information Society Technology program, aims to make use of board level optical interconnection in information systems practical and economical developing optoelectronic packaging technology compatible with standard electronic assembly processes. To demonstrate potential technology, we develop a demonstrator system that addresses most pressing problem contemporary computer architecture, memory...
The completed detailed design and initial phases of construction an optoelectronic crossbar demonstrator are presented. experimental system uses hybrid very large scale integrated optoelectronics technology whereby InGaAs-based detectors modulators flip-chip bonded onto silicon circuits. aims to demonstrate a 1-Tb/s aggregate data input/output single chip by means free-space optics.
A new Manchester code generator designed at transistor level is presented in this paper. This uses 32 transistors and has the same complexity as a standard D flip-flop. It intended to be used complex optical communication system. The main benefit of design use clock signal running frequency data. Output changes on rising edge falling clock. Simulations results show correct behavior up 1 Gbit/s data rate with 0.35 /spl mu/ CMOS technology within commercial temperature range.
A new kind of sigma-delta modulator made with a double integrator and bandpass stage is presented. It can reduce the oversampling ratio or increase bandwidth for constant sampling frequency compared equivalent complexity modulators.
The design, simulation and optimization of complex continuous-time (CT) circuits like Sigma-Delta modulators require large computation times when using only transistor-level analog simulators CADENCE Spectre or PSpice. Effective high-level system modeling should be considered in order to reduce the conception effort. However, closed-loop architecture characteristics technology requirements strictly observed on respective models. In this work, we present a design methodology resulted...
Time Interleaved ADCs (TIADCs) are a good solution to implement high sampling rate converters at moderate hardware cost. However, they suffer from mismatches between the ADC channels such as offset, gain, timing skew and possibly bandwidth mismatches. These have be corrected in order get sufficient performances converter. This paper presents classical calibration methods focuses on blind ones. Among those, both mixed analog-digital fully digital overviewed. By considering state-of-the-art of...
In order to reduce mismatch error of a DAC used in multibit delta-sigma some dynamic element matching (DEM) algorithms have been proposed before, from which data-weighted-averaging (DWA) method is more hardware efficient and widely used. Unfortunately, DWA technique loses its functionalities for periodic signals cannot be practically avoided. Many improvements suggested minimize band tone generated by algorithm, but they cause limited performance compared with an ideal first DEM. This paper...
Designing high-speed and low-power interconnects is a challenge for high performance computing applications, while silicon photonics can provide attractive solutions to perform highdensity communications. This paper presents an electro-optic transmitter operating at 20 Gbps (gigabit per second), as first step toward the demonstration of chip-to-chip optical links. The architecture based on dual-drive Mach-Zehnder interferometer co-integrated with 55-nm CMOS driver. Design optimizations...
Summary This article describes the design of integrated linear group delay filters for analog signal processing (ASP) applications and their implementation through constant‐resistance lattice bridged‐T networks. Unlike previously published works, our method uses a recursive procedure as basis synthesis suitable transfer function. Thanks to this method, with more characteristic flat magnitude response can be obtained. Two are designed in 0.13‐μm BiCMOS technology demonstrate method: balanced...
The high-speed optoelectronic memory system project is concerned with the reduction of latency within multiprocessor computer systems (a key problem) by use optoelectronics and associated packaging technologies. System demonstrators have been constructed to enable evaluation technologies in terms manufacturability. combines fiber, free space, planar integrated optical waveguide augment electronic processor components. Modeling simulation techniques were developed toward analysis design...
A new analysis and synthesis method for continuous time bandpass Delta-Sigma (/spl Delta//spl Sigma/) modulators is presented in this paper. This makes it possible to synthesize /spl Sigma/ from discrete topologies takes into account DAC+ADC delay rise time. Theoretically, high loop can be achieved non-ideal DAC used without effect on the performance of modulator, if some special feedback schematics are used.
In classical continuous-time band-pass sigma-delta (/spl Sigma//spl Delta/) modulators, the loop filter transfer function is a serial structure of biquadratic functions with high gains and quality factors. Unfortunately, such cannot be directly designed passive components. We propose parallel consisting in resonators low-order filter. The first branch cascade factors that guarantee gain band. second smooth guarantees /spl Delta/ stability out Filters characteristics are obtained thanks to an...
The overall resolution of a multibit delta-sigma modulator is limited by its internal digital-to-analog converter (DAC) nonlinearity caused mismatch errors. Recently, some dynamic element matching (DEM) methods were proposed to reduce errors, but they have serious problems instability or hardware complexity. Between DEM algorithms, tree-structured scheme (TDEM) possesses advantages in practical implementations surfers more from algorithm. Based on TDEM, this paper presents new shortened...
This paper demonstrates at the transistor level that sigma-delta modulators using passive filters can be good candidates for low power applications. The circuit we propose is composed of a latch-type self-timed comparator, switched capacitor filter and voltage reference with an additive dithering signal. Time-domain simulations show 10-bit resolutions expected usual over-sampling ratio values. enhancement provided by dither noise highlighted. global current consumption below 10 /spl mu/A 1...
Frequency-Band-Decomposition (FBD) is a good candidate to increase the bandwidths of ADC converters based on Sigma-Delta modulators, especially in context software radio, where very large bands need be converted. Each modulator processes part input signal band and followed by an adapted digital filter. A new solution, called Extended (EFBD) has been proposed during ANR VersaNUM project, allowing mismatches analog modulators without performance degradation, at price calibration stage. This...
This article presents a digital-enhanced radio frequency receiver for fast wide-band spectrum sensing. It is based on charge sampling and hybrid filter bank techniques. The method employed to design analog bandpass filters. Using analog-to-digital conversion improves the speed resolution of conversion. We propose use these techniques in combination frequency-division multiplexing with time-division an integrated, completely software reconfigurable reliable backend cognitive applications.
A methodology for synthesis and analysis of bandpass sigma-delta (/spl Sigma//spl Delta/) converters has been developed integrated in a Matlab toolbox. It allows the /spl Delta/ modulators with continuous time filters from discrete topologies. The method is based on discretization continuous-time models. uses simulator, more efficient than an analog simulator. All tools are included fully interactive, graphic open framework which user-developed modules can be added.
A methodology for the design of very low-cost medium resolution passive sigma-delta converters is proposed. This will be applied to a second-order modulator. Simulation results show performances that can expected from such converter.
This paper presents the design technique for a high speed sixth order bandpass continuous-time sigma-delta modulator in standard 0.35/spl mu/m CMOS technology. Three resonators are implemented parallel structure using highly linear operational transconductance amplifiers (OTA). Furthermore, an improved method employing two 3-bit flash converters as loop quantizer allows doubling sampling frequency. As consequence we can clocked at 1.2GHz allowing integration of passive LC-filters this...