A5061058896- Advancements in Semiconductor Devices and Circuit Design
- Semiconductor materials and devices
- Silicon Carbide Semiconductor Technologies
- Quantum and electron transport phenomena
- Radio Frequency Integrated Circuit Design
- Analog and Mixed-Signal Circuit Design
- Silicon and Solar Cell Technologies
- Advancements in PLL and VCO Technologies
- Low-power high-performance VLSI design
- Evolutionary Algorithms and Applications
- Advanced Multi-Objective Optimization Algorithms
- Metaheuristic Optimization Algorithms Research
University of Science and Technology of China
2019-2023
QuantumCTek (China)
2023
The development of large-scale quantum computing has boosted an urgent desire for the advancement cryogenic CMOS (cryo-CMOS), which is a promising scalable solution control and read-out interface bits. In this paper, 180 nm transistors are characterized modeled down to 4 K, impact low-temperature transistor performance variations on circuit design also analyzed. Based proposed model, we present CMOS-based 450-850 MHz clock generator operating at K applications. At 600 output frequency, it...
Previous cryogenic electronics studies are mostly at 77K and 4.2K. Cryogenic characterization of a 0.18μm standard bulk CMOS technology (operating voltages: 1.8V 5V) is presented in this paper. Several NMOS PMOS devices with different width to length ratios (W/L) were extensively tested characterized under various bias conditions sub-kelvin temperature. In addition dc characteristics, the kink effect current overshoot phenomenon observed discussed Especially, temperature shown for first...
Wide attention has been focused on cryogenic CMOS (cryo-CMOS) operation because of its promising improvement devices' and circuits' performance wide application prospects. However, hot carrier degradation (HCD) limits the long-term reliability cryo-CMOS. This article investigates HCD in 0.18 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> bulk at temperature down...
Cryogenic characterisation and modelling of CMOS technology (1.8 5 V) is presented in this Letter. Several P‐type MOS N‐type transistors with different width to length ratios were extensively characterised under various bias conditions at temperatures ranging from 300 K down 4.2 K. The authors extracted their fundamental physical parameters developed a compact model based on BSIM3V3. A simple subcircuit was built correct the kink effect. RMS error test results 3%.
Cryogenic characterization and modeling of 0.18um CMOS technology (1.8V 5V) are presented in this paper. Several PMOS NMOS transistors with different width to length ratios(W/L) were extensively characterized under various bias conditions at temperatures ranging from 300K down 4.2K. We extracted their fundamental physical parameters developed a compact model based on BSIM3V3. In addition I-V characteristics, threshold voltage(Vth) values, on/off current ratio, transconductance the MOS...
The extremely low threshold voltage ( V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH</sub> ) of native MOSFETs ≈ 0 V@300 K) is conducive to the design cryogenic circuits. Previous research on mainly focused standard (SVT) and (LVT) MOSFETs. In this article, we characterize within temperature range from 300 4.2 K. xmlns:xlink="http://www.w3.org/1999/xlink"> TH</sub> increases up ~0.25 (W/L = 10/ 10 μm) improved subthreshold swing (SS) 14.30...
Kink effect is a large obstacle for the cryogenic model of inversion-type bulk silicon MOSFET devices. This letter used two methods to correct kink effect: modified evolutionary strategy (MES) and dual-model modeling (BSIM3v3 EKV2.6). Both are based on principle effect. The first method considers impact ionization substrate current induced body (SCBE), other change freeze-out potential. By applying above methods, can be corrected improve agreement between simulation data measurement data,...
A novel power-efficient analog buffer at Liquid Helium Temperature (LHT) is proposed. The proposed circuit based on an input stage consisting of two complementary differential pairs to achieve rail-to-rail level tracking. Results simulation SMIC 0.18µm CMOS technology show the high driving capability and low quiescent power consumption cryogenic temperature. Operating single 1.4 V supply, achieves a slew-rate +36 V/µs -33.8 for 10 pF capacitive load. static only 55.7µW.
A novel power-efficient analog buffer at liquid helium temperature is proposed. The proposed circuit based on an input stage consisting of two complementary differential pairs to achieve rail-to-rail level tracking. Results simulation SMIC 0.18um CMOS technology show the high driving capability and low quiescent power consumption cryogenic temperature. Operating single 1.4 V supply, could a slew-rate +51 V/us -93 for 10 pF capacitive load. static only 79uW.
Abstract Optimization of analog circuits relies on engineers’ experience and intuition to find suitable parameters satisfy circuit specifications. This job is highly labor-intensive, repetitive, time-consuming, but the optimized sub-optimal. In this paper, evolutionary strategy proposed optimize design strategy. The filter designed by engineers operational amplifier with random generated instances’ are included, S gain dynamic power consumption respectively. simulation results show that can...
Previous cryogenic electronics studies are most above 4.2K. In this paper we present the characterization of a 0.18{\mu}m standard bulk CMOS technology(1.8V and 5V) at sub-kelvin temperature around 270mK. PMOS NMOS devices with different width to length ratios(W/L) tested characterized under various bias conditions temperatures from 300K It is shown that technology still working temperature. The kink effect current overshoot phenomenon observed Especially, in for first time. transfer...
This paper presents low power dissipation, phase noise ring oscillators (ROs) based on Semiconductor Manufacturing International Corporation (SMIC) 0.18{\mu}m CMOS technology at liquid helium temperature (LHT). First, the characterization and modelling of LHT are presented. The temperature-dependent device parameters revised model then shows good agreement with measurement results. oscillator is designed energy efficiency optimization by application forward body biasing (FBB). FBB proposed...
This paper presents low power dissipation, phase noise ring oscillators (ROs) based on Semiconductor Manufacturing International Corporation (SMIC) 0.18μm CMOS technology at liquid helium temperature (LHT). First, the characterization and modelling of LHT are presented. The temperature-dependent device parameters revised model then shows good agreement with measurement results. oscillator is designed energy efficiency optimization by application forward body biasing (FBB). FBB proposed to...
Wide attention has been focused on cryogenic CMOS (Cryo-CMOS) operation because of its wide application and the improvement performance. However, hot carrier degradation (HCD) becomes worsening at temperature, which affects reliability Cryo-CMOS. Therefore, this article investigates HCD in 0.18 um bulk temperature down to 4.2 K. Particularly, relationship between current overshoot phenomenon influence substrate bias are discussed. Besides, we predict lifetime device 77 K It is concluded that...