A5020359364- Analog and Mixed-Signal Circuit Design
- Advancements in Semiconductor Devices and Circuit Design
- Particle Detector Development and Performance
- Radio Frequency Integrated Circuit Design
- Advancements in PLL and VCO Technologies
- CCD and CMOS Imaging Sensors
- Particle Accelerators and Free-Electron Lasers
- Radiation Detection and Scintillator Technologies
- VLSI and Analog Circuit Testing
- Integrated Circuits and Semiconductor Failure Analysis
- Superconducting Materials and Applications
- Atomic and Subatomic Physics Research
- Advanced X-ray and CT Imaging
- Medical Imaging Techniques and Applications
- Analytical Chemistry and Sensors
- Neuroscience and Neural Engineering
- Semiconductor materials and devices
- Advanced Electrical Measurement Techniques
- Particle physics theoretical and experimental studies
- Nanowire Synthesis and Applications
European Organization for Nuclear Research
2019-2022
Alps Electric (Japan)
2020
Max Planck Society
2019
Universidade Nova de Lisboa
2010-2013
University of Lisbon
2011
Uninova
2010
Abstract Timepix4 is a 24.7 × 30.0 mm 2 hybrid pixel detector readout ASIC which has been designed to permit tiling on 4 sides. It consists of 448 512 pixels can be bump bonded sensor with square at pitch 55 µm. Like its predecessor, Timepix3, it operate in data driven mode sending out information (Time Arrival, ToA and Time over Threshold, ToT) only when hit above pre-defined programmable threshold. In this hits tagged time bin <200 ps record correctly incoming rates ∼3.6 MHz/mm /s....
A two-stage fully differential CMOS amplifier comprising inverters as input structures and employing self-biasing techniques is presented. The proposed benefits from an optimum compensation through time-domain optimization which permits achieving high energy efficiency. Moreover, it achieves the highest efficiency of its class although relies on a quasi-class-A topology, comparable to class-AB amplifiers. Detailed circuit analyses such differential-mode, common-mode feedback, noise, slew...
Power consumption is always a concern in the design of readout chips for hybrid pixel detectors. The Timepix3 chip capable dealing with up to 80 Mhits/cm2/sec and tagging each hit within time bin 1.56 ns. At full speed will consume 1.3 W. We consider how reduce power if rate and/or stamp precision not important. analog can be reduced by more than an order magnitude little impact on noise reducing bias current input transistor increasing return zero preamplifier. Digital might ∼ 6× lower...
This paper describes a novel two-stage fully-differential CMOS amplifier comprising two self-biased inverter stages, with optimum compensation and high efficiency. Although it relies on class A topology, is shown through simulations, that achieves the highest efficiency of its comparable to best AB amplifiers. Due self-biasing, low variability in DC gain over process, temperature, supply achieved. detailed circuit analysis, design methodology for optimization most relevant simulation results...
The Compact Linear Collider (CLIC) is a high-energy high-luminosity linear electron-positron collider under development. It foreseen to be built and operated in three stages, at centre-of-mass energies of 380 GeV, 1.5 TeV 3 TeV, respectively. offers rich physics program including direct searches as well the probing new through broad set precision measurements Standard Model processes, particularly Higgs-boson top-quark sectors. required for such specific conditions imposed by beam dimensions...
This brief presents an 8-bit 120-MS/s time-interleaved pipeline analog-to-digital converter (ADC) fully based on MOS discrete-time parametric amplification. The ADC, fabricated in a 130-nm CMOS logic process, features active area below 0.12 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , where only devices are used. Measurement results for 20-MHz input signal shows that the ADC achieves 39.7 dB of signal-to-noise ratio, 49.3...
This paper presents a reconfigurable architecture for coherent built-in self-testing (BIST) of high speed analog-to-digital converters (ADCs) with moderate resolutions. The proposed system is suited to be fully integrated the ADC and, besides low jitter clock reference, no other external quality generators are required. complete comprises two synchronized phase-locked loops (PLLs), one based on two-integrator oscillator capable providing distortion outputs and another relaxation squared...
Signals found in nature need to be converted the digital domain through analog-to-digital converters (ADCs) processed by means [1].For applications communication and measurement [2], [3] high conversion rates are required.With advances of CMOS technology, ADCs now well beyond gigasamples per second (GS/s) range, but only moderate resolutions required [4].These tested after fabrication and, if possible, during field operation.The test costs a very significant fraction their production cost...
In this paper we present a reconfigurable architecture for coherent built-in self-testing (BIST) of high speed IQ ADCs with moderate resolutions. The proposed system can be fully integrated the ADC and, besides low-jitter clock reference, no other external quality generators are required. A locked comprising first phase-locked loop (PLL) two linear outputs and second PLL squared output signal as well dedicated voltage-controlled oscillator (VCO) circuits. To illustrate simplicity solution,...
The time resolution of active pixel sensors whose timestamp mechanism is based on time-to-digital converters critically linked to the accuracy in distribution master clock signal that latches values across detector. network (CDN) delivers must compensate process-voltage-temperature variations reduce static errors (skew) and minimize power supply bounce prevent dynamic (jitter). To achieve sub-100-ps within detectors thus enable a step forward multiple imaging applications, latencies be...
This paper describes and compares some of the most energy area efficient self-calibration techniques reported over past years. Additional used to further improve power dissipation are briefly described as well. A robust mixed-signal technique is proposed, in which, multi-bit first stage ADC calibrated without requiring any modifications, long ideal conversion characteristic this known. novel Gaussian Noise Generator input analog stimulus and, on digital side, calibration algorithm does not...
A fast-settling two-stage completely self-biased amplifier (op amp) is presented. The op amp uses two amplifying stages and feedforward-regulated cascode transistors to achieve high dc gain, while maintaining a reasonable output swing high-frequency performance. Exhaustive simulation results over corners demonstrate that, after proper time-domain optimization of the proposed in 0.13-μm CMOS technology, very fast settling with accuracy 12 bits can be achieved, dissipating low power.
Time resolution of active pixel sensors whose time stamp mechanism is based on Time-to-Digital Converters critically linked to the accuracy in distribution master clock signal that latches timestamp values across detector. The Clock Distribution Network delivers must be robust non-idealities electronics, mainly process-voltage-temperature variations, device and layout mismatch noise coupling minimize static errors jitter. In order achieve sub-100ps within detectors thus enable a step forward...
S18ICTR-PHE 2016 each protocol to detect these deviations from the treatment plan is investigated by comparing planned and modified PET image.Several analysis methods are used: line profiles coupled field-directions, structural similarity index [1], gamma analysis.[2] Preliminary data shows that a difference in density best detected starting scan directly after first field.However, shifts perpendicular field directions better when done last field, due increased activity counting-rate.
The estimation of inter-channel mismatches in time-interleaved analog-to-digital converters (TI-ADCs) is a crucial step towards the compensation output errors inherent these converters. In this paper, we investigate fast, accurate and low-complexity method for static gain sample-time mismatches. proposed technique uses calibration signal generated on-chip through sinusoidal oscillator inserted into phase-locked loop (PLL), similarly as sampling clock usually high speed conversion systems. We...