A5021252999- Advanced Neural Network Applications
- Advanced Memory and Neural Computing
- Adversarial Robustness in Machine Learning
- Radiation Effects in Electronics
- Embedded Systems Design Techniques
- Parallel Computing and Optimization Techniques
- CCD and CMOS Imaging Sensors
- Distributed systems and fault tolerance
- Industrial Vision Systems and Defect Detection
- Anomaly Detection Techniques and Applications
- Fault Detection and Control Systems
- Neural Networks and Applications
- Software Reliability and Analysis Research
- Semiconductor materials and devices
- Interconnection Networks and Systems
- Gaze Tracking and Assistive Technology
- Software Testing and Debugging Techniques
- Music and Audio Processing
- Real-Time Systems Scheduling
- Embedded Systems and FPGA Design
- Seismology and Earthquake Studies
- Handwritten Text Recognition Techniques
- IoT-based Smart Home Systems
- Mechatronics Education and Applications
- Video Surveillance and Tracking Methods
Karlsruhe Institute of Technology
2021-2024
Institut für Informationsverarbeitung
2024
Enabling the use of Deep Neural Networks (DNNs) for time-series-based applications on low-power devices such as wearables opens up a wide range new features and services. However, inference requires an enormous amount operations to be performed by computing platform. In addition, Long Short-Term Memory (LSTM)-based networks require memory store internal cell state future calculations. this paper, we therefore propose hardware/software co-design based LSTM hardware accelerator architecture...
For AI-based systems in safety-critical domains, it is inevitable to understand the impact of random hardware faults affecting target accelerators. The high degree data reuse makes Deep Neural Network (DNN) accelerators susceptible significant fault propagation and hence hazardous predictions. Therefore, we present SiFI-AI, a simulation framework for injection DNN SiFI-AI proposes hybrid approach combining fast AI inference with cycle-accurate RTL simulation. Time-expensive only used...
Time series-based applications such as recognition of handwriting benefit from using Deep Neural Networks (DNNs) in terms accuracy and efficiency. Due to strict power memory limitations embedded platforms the Internet-of-Things (IoT), inference DNNs is usually performed on more powerful less constrained devices. However, mobile devices smartphones or tablets leads high system requirements. In this paper, we present our approach for distributing computational workload between sensor pen a...
In the future, it is expected that safety-critical and non-critical applications are executed on same hardware. Therefore, future hardware systems should be capable of providing runtime support for higher reliability requirements performance noncritical equally. this paper, we present a run-time adaptive cache with coarse-grained safety mechanism to tackle emerging challenge. For applications, operates in mode without any mechanisms. On other hand, checkpointing rollback feature fault...
ZuSE-KI-Mobil (ZuKIMo) is a nationally funded research project, currently in its intermediate stage. The goal of the ZuKIMo project to develop new System-on-Chip (SoC) platform and corresponding ecosystem enable efficient Artificial Intelligence (AI) applications with specific requirements. With ZuKIMo, we specifically target from mobility domain, i.e. autonomous vehicles drones. initial built by consortium consisting seven partners German academia industry. We SoC around novel AI...
Embedded image processing applications like multicamera-based object detection or semantic segmentation are often based on Convolutional Neural Networks (CNNs) to provide precise and reliable results. The deployment of CNNs in embedded systems, however, imposes additional constraints such as latency restrictions limited energy consumption the sensor platform. These requirements have be considered during hardware/software co-design Artifical Intelligence (AI) applications. In addition,...
Hardware accelerators for deep neural networks (DNNs) have established themselves over the past decade. Most developments worked towards higher efficiency with an individual application in mind. This highlights strong relationship between co-designing accelerator together requirements of application. Currently a structured design flow, however, it lacks tool to evaluate DNN embedded System on Chip (SoC) platform.To address this gap state art, we introduce FLECSim, framework that enables...
Distributed systems can be found in various applications, e.g., robotics or autonomous driving, to achieve higher flexibility and robustness. Thereby, data flow centric applications such as Deep Neural Network (DNN) inference benefit from partitioning the workload over multiple compute nodes terms of performance energy-efficiency. However, mapping large models on distributed embedded is a complex task, due low latency high throughput requirements combined with strict energy memory...
Neural networks achieve high accuracy in tasks like image recognition or segmentation. However, their application safety-critical domains is limited due to black-box nature and vulnerability specific types of attacks. To mitigate this, methods detecting out-of-distribution adversarial attacks parallel the network inference were introduced. These are hard compare because they developed for different use cases, datasets, networks. fill this gap, we introduce EFFECT, an end-to-end framework...
Convolutional Neural Networks (CNNs) show tremendous performance in many Computer Vision (CV) tasks like image segmentation crucial to autonomous driving. However, they are computationally demanding and usually not robust corruptions weather influences. In this paper, we introduce our mixed-precision inference method overcome these two challenges. Therefore, enable CNN execution on modern embedded system chips (SoC) that feature a DNN accelerator reconfigurable fabric. case of change, can...
A key challenge in computing convolutional neural networks (CNNs) besides the vast number of computations are associated numerous energy-intensive transactions from main to local memory. In this paper, we present our methodical approach maximize and prune coarse-grained regular blockwise sparsity activation feature maps during CNN inference on dedicated dataflow architectures. Regular that fits target accelerator, e.g., a systolic array or vector processor, allows simplified resource...
In this paper, we present a novel hardware approach, which allows simultaneous program execution in parallel to state transfer. We introduce an interleaved replication methodology and corresponding processor architecture. Our is applicable for fast context switches are of crucial importance mixed criticality systems. To enable our directly on the level propose appropriate On architecture implement various transfer strategies investigate them representative workloads. experiments demonstrate...