A5036023193- Semiconductor materials and devices
- Ferroelectric and Negative Capacitance Devices
- Advancements in Semiconductor Devices and Circuit Design
- Ferroelectric and Piezoelectric Materials
- MXene and MAX Phase Materials
- Integrated Circuits and Semiconductor Failure Analysis
- Analog and Mixed-Signal Circuit Design
- Magnetic Properties and Synthesis of Ferrites
- Wireless Communication Networks Research
- Magneto-Optical Properties and Applications
- Advanced Wireless Network Optimization
- Thermal Expansion and Ionic Conductivity
- Electronic Packaging and Soldering Technologies
- Advanced ceramic materials synthesis
- VLSI and FPGA Design Techniques
- Chemical and Physical Properties of Materials
- Real-time simulation and control systems
- 2D Materials and Applications
- Scientific Measurement and Uncertainty Evaluation
- Advancements in PLL and VCO Technologies
- Advancements in Battery Materials
- Copper Interconnects and Reliability
- Silicon Carbide Semiconductor Technologies
- Calibration and Measurement Techniques
- Acoustic Wave Resonator Technologies
Koneru Lakshmaiah Education Foundation
2023-2024
Indian Institute of Information Technology Design and Manufacturing Jabalpur
2020-2022
Global Hospitals
2019
Atal Bihari Vajpayee Indian Institute of Information Technology and Management
2016
Dr. Bhim Rao Ambedkar University
2009
Thapar Institute of Engineering & Technology
2008
Abstract One of the severe issues downscaling semiconductor devices is threshold voltage reduction which significantly increases leakage current. Thus, high (HVT) techniques are required to bring down hike for improved performances. In this paper, first time, we investigate analog/radio frequency (RF) and linearity performances silicon (Si) FinFET by employing HVT techniques. Using well-calibrated technology computer aided design models, mitigate current, analyzed following approach get HVT:...
In the incessant search to overcome power densities and energy efficient limitations, performance matrix of emerging electronic devices are being explored inevitably find alternatives MOSFETs. We investigated compared delay matrices fin-shaped FET negative capacitance FinFET (NC-FinFET) based circuits designed on same technology node. The improvement in NC-FinFET CMOS is enhanced due capacitance's DIBL by employing a industry standard BSIM-CMG model. After analyzing at device-level, detailed...
Phase transition FinFET (PT-FinFET) is an emerging steep slope device that utilizes phase material (PTM) at the source of host to achieve switching and boost <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${I}_{ \mathrm{\scriptscriptstyle ON}}/{I}_{ OFF}}$ </tex-math></inline-formula> ratio compared conventional transistors. Due nonzero notation="LaTeX">$\rho _{\text {MET}}$ assisting PTM, PT-FinFET...
An enormous study is being carried out in the field of emerging steep slope devices, specifically on negative-capacitance-based and phase transition-based devices. This article investigates action ferroelectric (FE) transition material (PTM) a hybrid device, negative-capacitance-assisted FinFET (NC-PT-FinFET). We encounter several unique phenomena resulting from this unified provide valid arguments based these observations. A significant enhancement differential gain transconductance,...
In this article, we have performed a comprehensive study into the Phase Transition Material based FinFET(PT-FinFET) device's capabilities for low-power, energy-efficient applications through device circuit co-design perspective. Addressing its drawback at and level novel design known as Negative Capacitance FinFET(NC-PTFinFET) is proposed by incorporating ferroelectric material layer gate stack of PTFinFET. The outperforms PTFinFET FinFET in terms SS ON–OFF current ratio level, well power...
In this paper, a detailed evaluation of negative capacitance FinFET (NC-FinFET) based volatile static random access memory (6T-NCSRAM) is carried out by utilizing L-K equation for ferroelectric and calibrated BSIM-CMG model with 14 nm conventional to form NC-FinFET. Static dynamic behavior NC-FinFETs explored evaluated at different thickness. At supply voltage scaling, important SRAM performance metrics such as stability operation condition (hold, read write mode) standby leakage power were...
A unique NFET device with specially treated region underneath the buried-oxide (BOX) in state-of-the-art 22 nm FD-SOI technology (GLOBALFOUNDRIES' 22FDX <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">®</sup> technology), displays excellent switch performance for wide frequency range. Very gradual response of insertion-loss (IL) makes ideal choice 80 GHz applications sub-2 dB IL. Other RF figure merits (FoMs) like cut-off fT (351 GHz) and...
Negative Capacitance Field Effect Transistors are well known for their superior performance over MOSFET and a viable candidate to succeed the baseline FET in time ahead. We have studied of 32 nm planar with doped hafnium dioxide as ferroelectric material. The functioning NCFET is entirely dependent on equivalence between MOS capacitance. Our simulation results clearly indicated that Sr HfO2 has close capacitance matching capacitance, when compared other dopant material (Si, Al Zr). This also...
Modern wearable devices demand low power high performance medical signal monitoring to achieve efficient and reliable health-care services. The electrocardiogram (ECG) which is used diagnose heart diseases requires 24 hour monitoring. Efficient VLSI implementation of lossless ECG encoder the critical requirement in wireless health care This paper presents an area that utilizes a single stage Huffman table provide compressed data. In proposed architecture, range data encoded via small whereas...
This paper describes a holistic design and simulation tool deployed for virtual prototyping of SiC power modules. The module designer proceeds from concept to prototype in logical comprehensive flow. Starting with simple 2D DXF the Direct Bond Copper (DBC), is designed through die selection placement, layer material property declaration, electrical connectivity, external port definition. Automated 3D model generation carried out advanced Ansys scripting techniques. Multiple levels are...
In this article, we have studied passive voltage amplification in FE-FE-DE heterostructure. We stacked two different ferroelectric oxides; one is second-order transition material (continuous material) and the other first-order (discontinuous material). Both materials polarities of anisotropy constant (β), which tuned by varying thickness thus leads to its cancellation. The nullification will reduce non-linearity oxide provide efficient matching between dielectric capacitance, turn delivers...
Electric-thermal modelling and simulation of power electronics modules is critical, yet time consuming error prone task. Automation tasks helps reduce while producing reliable consistent results. A web-based tool, MFIT, has been previously developed to cover the module process. MFIT starts with an existing 2D drawing DBC (Direct Bond Copper) substrate leadframe constructs. The user then places dies from a preexisting die database. wire clip subsequently executed. External input out signal...
Linearity and intermodulation distortion are very crucial parameters for RFICs design. Therefore, in this work, a detailed comparative analysis on linearity of single metal (SMG) double (DMG) gate junction less transistor (JLT) is done using TCAD silvaco suite. Furthermore, the effects temperature fluctuation, length variation, material engineering performance both devices also studied. A few significant figures merit, including Voltage Intercept Point 2 (VIP2), 3 (VIP3), Third Order Power...
Improved recycling folded cascode(RFC) operational transconductance amplifier(OTA) is presented in this brief. Performance of the proposed OTA significantly enhanced comparison to conventional cascode(FC) and by employing a dynamic current boosted adaptive bias circuit positive feedback with an improved mirror. The design simulated cadence virtuoso analog environment SCL <tex>$0.18\ \mu m$</tex> standard CMOS technology. Simulation results indicate that achieves slew rate (SR), gain...
The present paper reports the optimization and analysis of interconnect parameters such as ground coupling capacitance which play very important roll in design development future microelectronics devices. Here, we have optimized along with variation dielectric thickness interwire spacing respectively. It has been observed that increases increase spacing. is also find out decreases simultaneously thickness.
The present work reports the development of a Mn-Zn ferrite material suitable for power applications with core losses amounting to 529 and 296 kW.m−3 at operating frequency 100 kHz driving flux density 200 mT 25° 100°C respectively. Power loss values below 400 in wide temperature range above 65°C make it most promising candidate regular switching supplies, as well main transformers DC-DC converters automotive applications.