This paper focuses on the low-computation harmonic-analysis procedure with sufficient suppression of spectral leakage and picket-fence effect. The interpolated FFT algorithm based minimized sidelobe window is considered, its calculate formulas are given, which free solving high-order equations. implementation proposed in digital-signal-processor (DSP) three-phase harmonic ammeter also introduced. has major advantages that for parameters can be easily implemented by hardware multipliers,...

A novel approach to harmonic analysis for industrial power systems based on windowed fast Fourier transform is presented. First, the desirable sidelobe window (DSW) constructed through self-convolution of maximum decay (MDW) in time domain. Then, system signal parameters, i.e., frequency, phase, and amplitude, are calculated by DSW-based discrete phase difference correction algorithm. It has been shown that spectral leakage interferences can be reduced considerably weighting samples with DSW...

Views Icon Article contents Figures & tables Video Audio Supplementary Data Peer Review Share Twitter Facebook Reddit LinkedIn Tools Reprints and Permissions Cite Search Site Citation Xiaojing Mu, Piotr Kropelnicki, Yong Wang, Andrew Benson Randles, Kevin Tshun Chuan Chai, Hong Cai, Yuan Dong Gu; Dual mode acoustic wave sensor for precise pressure reading. Appl. Phys. Lett. 15 September 2014; 105 (11): 113507. https://doi.org/10.1063/1.4896025 Download citation file: Ris (Zotero) Reference...

Monolithic integration of synthetic aperture radar (SAR) transceiver with small size, lightweight, and low power consumption is suitable for uploading to a compact unmanned aerial vehicle (UAV) SAR imaging. This paper presents monolithic frequency-modulated continuous-wave (FMCW) that works at Ku-band centers 15 GHz. Techniques address the special requirements UAV are proposed. A digital-tunable mixed-signal-mode FMCW chirp synthesizer designed be efficient, provide tunable rate, enable...

A Ku-band wideband power amplifier (PA) for frequency modulated continuous wave (FMCW) radar application is proposed and implemented in 65-nm bulk CMOS technology. To obtain low group delay, amplitude ripple, wide bandwidth, the transformer inductor-based matching network designed to meet requirements. Including pads, PA occupies a compact chip area of 0.62 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . Consuming 118-mA current...

High-data-rate short-range communication and image systems beyond 100GHz impose crucial requirements on signal sources, demanding superior purity stability. Using frequency multipliers with high efficiency multiplication factor to generate the N <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sup> harmonic that is phase-locked by a PLL at fundamental provides an alternative solution. The desired in active multiplier can be generated using...

Compared with the conventional central shunt active power filter (SAPF), modular designed SAPF can track harmonics more precisely and quickly a compact expandable structure, which makes it better solution for harmonic mitigation. But there are very few paper discussed about modeling parallel resonance issues of system. This provides three-level SAPF, aiming to guide design research control method. First, simplified is proposed based on averaging impedance small signal linearization...

This letter proposes a reconfigurable bias choke topology power amplifier (PA) that achieves high power-added efficiency (PAE) and multioctave bandwidth in nonuniform distributed PA (NDPA) designs. The proposed extended bandwidth, optimized matching networks, improved PAE. 0.8–18 GHz frequency NDPA (FRNDPA) is configured for two subbands, 0.8–4.5 4.5–18 GHz. chip fabricated using 0.15- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">...

A folded XOR gate (FXOR) phase detector (PD) is proposed for millimeter-wave (mmW) SiGe integer- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$N$ </tex-math></inline-formula> phase-locked loops (PLLs) to relax the tradeoff between PLL loop bandwidth and reference spur rejection. With four current-reuse gates jointly participated in detection, generated by each neutralizes that from its complementary...

This paper demonstrates a fully integrated high-output-power, ultra-wideband, and reconfigurable power amplifier. Based on the improved non-uniform distributed structure, drain bias choke module, gate module dumping load are proposed. The amplifier has an improvement in input matching, bandwidth, output power-added efficiency (PAE). Fabricated 0.25um GaN process, Measurement results show 37.3-to-39.1 dBm saturated (P <inf xmlns:mml="http://www.w3.org/1998/Math/MathML"...

A compact reconfigurable CMOS bandpass filter (BPF) with high selectivity is proposed using transformer-type resonators in this article. The resonator constructed by a transformer loaded parallel varactors for frequency tuning, and two are then added across primary wind secondary coupling tuning. With the structure, one formed inside another resonator, thus fully utilizing chip area resulting miniaturized structure. Magnetic electrical couplings within facilitate bandwidth (BW) quality...

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Using a quadrature XOR-gate (QXOR) reduces the second order harmonic term at output, making it suitable to be used as phase/frequency detector in high-frequency phase-locked loops. This paper introduces 320 GHz PLL employing QXOR cancel reference spur, suppress in-band noise, and also power consumption of frequency tracking loop (FTL). The beat FTL enables lock (LD) search right band for VCO operation. proposed was implemented IHP 0.13 µm SiGe BiCMOS process. Measured results show that...

This letter presents a temperature compensated oscillator for clock generation across wide range. The proposed technique deploys the characteristics of constant-biased varactors to nullify overall oscillator's coefficient (TC), thereby reducing drift effect on frequency output. Fabricated CMOS technology, 2.09 GHz-gm-LC sees mere from -20 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">°</sup> C 120 C. consumes 10.9 mW at 1.4 V supply, with...

A high gain decibel (dB)-linear programmable amplifier (PGA) for a synthetic aperture radar (SAR) receiver is presented in this paper. The proposed PGA employs binary-weighted switching array as pseudo-exponential function to achieve large dynamic range. current compensation circuit fine step cell decrease error. This has been implemented 65 nm CMOS technology embed ding SAR receiver. Measurement results show that the exhibits dB-linear range of 60 dB from 10.47 69.63 with error less than...

This letter presents a new monolithic oscillatory circuit that is applicable to different microelectromechanical systems (MEMS)/crystal resonators. The proposed technique cascades tuned amplifiers (TAs) with varactors in their LC-tanks. By adjusting the bias voltage of varactors, center frequencies TAs can be controlled change loop response oscillator. Using this approach, oscillation conditions precisely attained for resonant frequencies. Tunable negative resistance realized through biasing...

An automatic inductor design process is helpful to reduce the cycle of radio frequency (RF) integrated circuit (IC). This paper proposed an efficient synthesis-analysis machine (SAM) for on-chip synthesis and modeling, as well dataset generation (ADG) topology artificial neural networks (ANNs) training dataset. The SAM consists a ANN, two analysis ANNs self-inspection (SIM). For given request, synthesizes layout first, followed by analyzing performance automatically, finally improves...

In this paper, an on-chip wideband bandpass filter (BPF) with high frequency selectivity and low insertion loss is proposed using gallium arsenide (GaAs) integrated passive device (IPD) technology. Multiple transmission zeros can be provided by the capacitors loaded on series parallel LC resonators for design. Comparing state-of-the-art BPFs, design has advantages of loss. The final centered at 1.93 GHz 3-dB fractional bandwidth 64.2% demonstrated, which exhibits excellent shape factor...

This paper describes circuit techniques for the implementation of low-voltage CMOS integrators continuous-time filters. A prototype sixth-order Butterworth lowpass filter with two programmable zeros was designed and developed to demonstrate proposed techniques. The is suitable magnetic disk read channel applications achieves a 4.8:1 bandwidth tuning range maximum -3 dB 130 MHz. spurious free dynamic an input signal 300 mV peak-to-peak differential greater than 40 dB. alone consumes mW from...

A Ku-band wideband power amplifier (PA) for FMCW radar application is proposed and implemented in 65-nm bulk CMOS technology. The PA consists of 3 stages class AB amplifiers to achieve high gain efficiency. To obtain low group delay (GD), amplitude ripple wide bandwidth, transformer inductor based matching network designed meet the requirements. Including pads, occupies a compact chip area 0.62 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML"...

A high efficiency non-uniform distributed power amplifier (NDPA) based on a 0.15 μm Gallium Nitride (GaN) HEMT process is proposed. The contains eight amplification cells and uses artificial transmission line theory to design the drain with decreasing characteristic impedance. To improve of amplifier, class AB biased designed for optimum impedance matching using networks. electromagnetic simulation results show that small signal gain more than 12.6 dB saturated output (P <inf...