A5101784204- Numerical Methods and Algorithms
- Digital Filter Design and Implementation
- Probabilistic and Robust Engineering Design
- Structural Health Monitoring Techniques
- Advanced Multi-Objective Optimization Algorithms
- Parallel Computing and Optimization Techniques
- Advanced SAR Imaging Techniques
- Video Coding and Compression Technologies
- Fault Detection and Control Systems
- Advanced Data Compression Techniques
- IoT-based Smart Home Systems
- Cloud Computing and Resource Management
- CCD and CMOS Imaging Sensors
- Distributed and Parallel Computing Systems
- Sentiment Analysis and Opinion Mining
- Computational Physics and Python Applications
- Reliability and Maintenance Optimization
- Wireless Sensor Networks and IoT
- Energy Efficient Wireless Sensor Networks
- Structural Response to Dynamic Loads
- Neural Networks and Applications
- PAPR reduction in OFDM
- Advanced Adaptive Filtering Techniques
- Optimal Experimental Design Methods
- Embedded Systems Design Techniques
National University of Defense Technology
2022-2024
Beijing Zhenxing Metrology & Measurement Institute
2020
Beijing Institute of Radio Metrology and Measurement
2020
Beijing Institute of Technology
2017-2020
Beijing University of Posts and Telecommunications
2019
Xi'an Jiaotong University
2009
This paper presents the design methodology and implementation of reconfigurable coordinate rotation digital computer (CORDIC) architecture that can be configured to operate in different modes rotations achieve singleprecision floating point division, multiplication square-root operations. Through introducing pre- post-processing, float-point operations integrated into a unified CORDIC iteration procedure. According characteristics operations, we propose pipeline-parallel mixed optimize...
With the development of satellite load technology and very large-scale integrated (VLSI) circuit technology, onboard real-time synthetic aperture radar (SAR) imaging systems have facilitated rapid response to disasters. The state-of-the-art System-on-Programmable-Chip (SoPC) technique, associated with embedded processor other function modules, provides a potential solution satisfy all constraints. However, improvement processing efficiency imagery granularity, implement an entire SAR using...
This paper presents a unified reconfigurable coordinate rotation digital computer (CORDIC) processor for floating-point arithmetic. It can be configured to operate in multi-mode achieve variety of operations and replaces multiple single-mode CORDIC processors. A pipeline-parallel mixed architecture is proposed adapt different operations, which maximises the sharing common hardware circuit achieves area-delay efficiency. Compared with previous processors, consumption resources greatly...
In the multi-mode SAR imaging processing targeted in this paper, FFT requirement granularity ranges from 1024 to 32768. Therefore, paper mainly describes method of implementing reconfigurable and variable-level units using radix-2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</sup> , By analyzing comparing radix 2 algorithm, xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> is selected as basis single-channel butterfly, range point...
In this paper, we demonstrate an achievable implementation of Doppler parameters estimation engine. Taking advantage FPGA, a highly parallelized and reconfigurable structure with unified calculation is adopted. We build prototype using single off-the-shelf Xilinx XC6VSX315T FPGA to verify the proposed method in 16384 ×16384 SAR imaging process. The experiment result can achieve more than 20x time speedups over CPU-based solution, hardware resources be balanced.
GridDEV is a DEVS-based platform for evaluation of service grid. Through the analysis SOA, we characterize important features grid and select four components as base modeling. With DSDEVS, this paper models basic selected, well relationships between them. As result, model fully formalizes system;hence facilitates design optimization services. Based on model, map DEVS component into elements simulator development library SimGrid, construct performance reliability evaluation.
This paper presents a unified reconfigurable coordinate rotation digital computer (CORDIC) processor for floating-point arithmetic. It can be configured to operate in multi-mode achieve variety of operations and replaces multiple single-mode CORDIC processors. A pipeline-parallel mixed architecture is proposed adapt different operations, which maximizes the sharing common hardware circuit achieves area-delay-efficiency. Compared with previous processors, consumption resources greatly...
To design a high-precision and low-complexity FFT/IFFT processor architecture, the optimum bit sizing technique in each stage is usually adopted. However, it difficult to provide an accurate, fast word length scheme due diversity of FFT algorithms complexity circuit structure. In this paper, we focus on widely-used radix-2k Decimation-In-Frequency (DIF) Fast Fourier Transform (FFT) algorithm. Based our previous research fixed-point Signal-to-Quantization-Noise Ratio (SQNR) assessment,...
The high-fidelity data (HF) referring to the test from real experiments can more accurately reflect performance indicators of workpieces for reliability analysis in engineering. Due limited cost, enough HF is difficult be collected meet requirement analysis. Alternatively, a large amount low-fidelity (LF) experimental simulation integrated with achieve estimates high precision. Existing literatures have studied this problem and made some progress, but model rather complicated solving...
Since the physical structure and mathematical models are more complex, reliability analysis in practical engineering can be expensive difficult. A two-level multifidelity metamodel method for is introduced. Following surrogate model most of relevant works, low-fidelity data high-fidelity integrated by co-Kriging model. Besides, also provide an approximation initial performance function. Bayesian adopted solution a hybrid Markov chain Monte Carlo (MCMC) sampling algorithm proposed....