A5082687228- Advanced Battery Technologies Research
- VLSI and Analog Circuit Testing
- Advancements in Battery Materials
- Low-power high-performance VLSI design
- Gas Sensing Nanomaterials and Sensors
- CCD and CMOS Imaging Sensors
- Integrated Circuits and Semiconductor Failure Analysis
- Advanced Battery Materials and Technologies
- Advanced battery technologies research
- biodegradable polymer synthesis and properties
- Molten salt chemistry and electrochemical processes
- Electronic Packaging and Soldering Technologies
- Chemistry and Chemical Engineering
- Aerosol Filtration and Electrostatic Precipitation
- Radio Frequency Integrated Circuit Design
- Analytical Chemistry and Sensors
- Catalysis for Biomass Conversion
- Advanced Manufacturing and Logistics Optimization
- Advanced DC-DC Converters
- 3D IC and TSV technologies
- Advancements in Photolithography Techniques
- Advancements in Semiconductor Devices and Circuit Design
- Semiconductor materials and interfaces
- Transition Metal Oxide Nanomaterials
- Extraction and Separation Processes
IBM (Germany)
1986-2007
Poughkeepsie Public Library District
2006
IBM (United States)
1982
United States Army
1969
United States Department of the Army
1968
Abstract Polyethylene furanoate (PEF) is a biobased plastic, similar to synthetic polyethylene terephthalate (PET), which produced from the platform chemical 2,5‐hydroxymethylfurfural (HMF). Much of literature surrounding PEF focused on unit processes, with little regard for their sustainability and economic viability. In this comprehensive critical review, entire process production, feedstock polymerization upstream applications, critically examined. Identification individual pathways...
The 65nm CELL Broadband Enginetrade design features a dual power supply, which enhances SRAM stability and performance using an elevated array-specific while reducing the logic consumption. Hardware measurements demonstrate low-voltage operation reduced scatter of minimum operating voltage. chip operates at 6GHz 1.3V is fabricated in CMOS SOI technology.
In this paper, we describe an advanced optical diagnostic technique used for diagnosing the IBM z990 eServer microprocessor (Slegel et al., 2004). Time-to-market pressure demands quick turnaround time and high resolution while ever increasing design complexity, density, cycle time, shrinking technologies dramatically add difficulties to diagnostics. Although design-for-test (DFT) design-for-diagnostics (DFD) features are implemented in latest microprocessors help easing efforts, they may...
Cadmium‐air cells have been developed that deliver 45–50 whr/lb at the rate of discharge. The major failure modes cadmium‐air system are: loss capacity by cadmium anode, shorting penetration, poisoning air‐cathode a soluble species, electrocatalytic activity during prolonged cycling, and water evaporation through cathode pores and/or cell vent. It has determined anode can be prevented addition or extender into active structure removal from influent air stream. was found penetration separator...
A 1.0-/spl mu/m CMOS technology with three layers of metal is used to implement a high-density master image that contains logic and RAMs. The allows the use more than 1,000,000 transistors. hierarchical design methodology described. This chip offers variable-sized physical partitions RAM macros. Fixed area sizes locations for macros are not necessary. Density performance custom chips approached by described significantly lower development cost time.
This paper describes high speed SRAMs with read access time below 500 ps and a cycle around 2 GHz in 1.5 V, 0.18 /spl mu/m partially depleted (PD) SOI CMOS technology. The also provides the robust designs to improve performance functionality PD SOI. highlights of are optimized timing for pseudostatic circuits, novel design sense amplifier, techniques at temperatures cell stability. Also full functional SRAM (Directory, L1 Cache other SRAMs) hardware yields is demonstrated by providing...
A 1.0 μm CMOS technology with 3 layers of metal is used to implement a high density Master Image that contains LOGIC and RAMs. The allows the usage even more than 1,000,000 transistors. hierarchical design methodology described. This chip offers variable sized physical partitions RAM macros. No fixed area sizes locations for macros are necessary. Chip performance oustomized chips approached by described at significantly lower development cost time.