Sorav Bansal

ORCID: 0009-0004-2006-9635
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About
Contact & Profiles
Research Areas
  • Parallel Computing and Optimization Techniques
  • Cloud Computing and Resource Management
  • Advanced Data Storage Technologies
  • Mobile Ad Hoc Networks
  • Formal Methods in Verification
  • Wireless Networks and Protocols
  • Software Testing and Debugging Techniques
  • Logic, programming, and type systems
  • Cooperative Communication and Network Coding
  • Security and Verification in Computing
  • Constraint Satisfaction and Optimization
  • Distributed and Parallel Computing Systems
  • Metaheuristic Optimization Algorithms Research
  • Natural Language Processing Techniques
  • Software Engineering Research
  • Radiation Effects in Electronics
  • Energy Efficient Wireless Sensor Networks
  • Advanced Wireless Network Optimization
  • Cloud Computing and Remote Desktop Technologies
  • Distributed systems and fault tolerance
  • Software-Defined Networks and 5G
  • Personal Information Management and User Behavior
  • Embedded Systems Design Techniques
  • Computer Graphics and Visualization Techniques
  • Software Reliability and Analysis Research

Indian Institute of Technology Delhi
2013-2024

Stanford University
2003-2008

Laboratoire d'Informatique de Paris-Nord
2008

IBM Research - India
2003-2006

Indian Institute of Technology Indore
2002

Ad hoc networks rely on the cooperation of nodes participating in network to forward packets for each other. A node may decide not cooperate save its resources while still using relay traffic. If too many exhibit this behavior, performance degrades and cooperating find themselves unfairly loaded. Most previous efforts counter behavior have relied further between exchange reputation information about other nodes. a observes another correctly, it reports observation who then take action avoid...

10.48550/arxiv.cs/0307012 preprint EN other-oa arXiv (Cornell University) 2003-01-01

Peephole optimizers are typically constructed using human-written pattern matching rules, an approach that requires expertise and time, as well being less than systematic at exploiting all opportunities for optimization. We explore fully automatic construction of peephole brute force superoptimization. While the optimizations discovered by our system may be general counterparts, has potential to automatically learn a database thousands millions optimizations, in contrast hundreds found...

10.1145/1168857.1168906 article EN 2006-10-20

This paper presents the initial design and performance study of MACA-P, a RTS/CTS based MAC protocol that enables simultaneous transmissions in multihop ad-hoc wireless networks. Providing such low-cost high access networks is an important enabler pervasive computing. MACA-P set enhancements to 802.11 DCF allows parallel many situations when two neighboring nodes are either both receivers or transmitters, but receiver transmitter not neighbors. Like 802.11, contains contention-based...

10.1109/percom.2003.1192780 article EN 2004-01-23

We present a new scheme for performing binary translation that produces code comparable to or better than existing translators with much less engineering effort. Instead of hand-coding the from one instruction set another, our approach automatically learns rules using superoptimization techniques. have implemented PowerPC-x86 translator and report results on small large computeintensive benchmarks. When compared native compiler, translated achieves median performance 67% benchmarks in some...

10.5555/1855741.1855754 article EN Operating Systems Design and Implementation 2008-12-08

Effective huge page management in operating systems is necessary for mitigation of address translation overheads. However, this continues to remain a difficult area OS design. Recent work on Ingens uncovered some interesting pitfalls current strategies. Using both access patterns discovered by the kernel and fine-grained data from hardware performance counters, we expose problematic aspects In our system, called HawkEye/Linux, demonstrate alternate ways issues related performance, fault...

10.1145/3297858.3304064 article EN 2019-04-04

A router in wired network typically requires multiple interfaces to act as a or forwarding node. In an ad-hoc multi-hop wireless on the other hand, any node with interface card can operate node, since it receive packet from neighboring do route lookup based packet's destination IP address, and then transmit another using same interface. This paper investigates combined medium access next-hop address fixed length labels (instead of addresses), which allows entire operation be executed within...

10.1145/570790.570797 article EN 2002-09-28

This paper presents the detailed design and performance analysis of MACA-P, a RTS/CTS based MAC protocol, that enables simultaneous transmissions in wireless mesh networks. The IEEE 802.11 DCF prohibits any parallel transmission neighborhood either sender or receiver (of an ongoing transmission). MACA-P is set enhancements to allows situations when two neighboring nodes are both receivers transmitters, but transmitter not neighbors. terms system throughput obtained through simulation...

10.1109/broadnets.2004.29 article EN 2004-12-23

The concept of a forwarding node, which receives packets from upstream nodes and then transmits these to downstream nodes, is key element any multihop network, wired or wireless. While high-speed IP router architectures have been extensively studied for networks, the "wireless router" has not addressed so far. We examine limitations IEEE 802.11 MAC protocol in supporting low-latency high-throughput datapath comprising multiple wireless LAN hops. first propose architecture that uses MPLS with...

10.1109/mwc.2003.1241091 article EN IEEE Wireless Communications 2003-10-01

We study the performance metrics associated with TCP-regulated traffic in multi-hop wireless networks that use a common physical channel (e.g., IEEE 802.11). In contrast to earlier analyses, we focus simultaneously on two key operating - energy efficiency and session throughput. Using analysis simulations, show how these are strongly influenced by radio transmission range of individual nodes. Due tradeoffs between packet likelihood retransmissions, total consumption is convex function number...

10.1109/infcom.2002.1019262 article EN 2003-06-25

An interesting feature of IEEE 802.11 wireless LAN cards is that they support multiple transmission modes. For example, the 802.11b four modes I, 2, 5.5 and 11 Mbps, whereas, 802.11a eight modes, up to a maximum 54 Mbps. In this paper, we study layer protocols over multi-rate multi-hop networks attempt answer question whether higher bandwidth links necessarily outperform lower in these networks. We examine by taking into account transport such as TCP UDP. While network capacity topic active...

10.1109/wcnc.2004.1311548 article EN 2004-10-19

A router in wired network typically requires multiple interfaces to act as a or forwarding node. In an ad-hoc multi-hop wireless on the other hand, any node with interface card can operate node, since it receive packet from neighboring do route lookup based packet's destination IP address, and then transmit another using same interface. This paper investigates combined medium access next-hop address fixed length labels (instead of addresses), which allows entire operation be executed within...

10.1145/570796.570797 article EN 2002-01-01

Previous approaches to systematic state-space exploration for testing multi-threaded programs have proposed context-bounding and depth-bounding be effective ranking algorithms multithreaded programs. This paper proposes two new metrics rank thread schedules exploration. Our are based on characterization of a concurrency bug using v (the minimum number distinct variables that need involved the manifest) t threads among which scheduling constraints required manifest bug). algorithm is...

10.1145/2483760.2483764 article EN 2013-07-15

Dynamic binary translation (DBT) is a powerful technique with several important applications. System-level translators have been used for implementing Virtual Machine Monitor [2] and instrumentation in the OS kernel [10]. In current designs, performance overhead of on kernel-intensive workloads high. e.g., over 10x slowdowns were reported syscall nanobenchmark [2], 2-5x lmbench microbenchmarks These overheads are primarily due to extra work required correctly handle mechanisms like...

10.1145/2517349.2522718 article EN 2013-10-08

Programming hybrid CPU-GPU clusters is hard. This paper addresses this difficulty and presents the design runtime implementation of Unicorn-a parallel programming model for clusters. In particular, proves that efficient distributed shared memory style programing possible its simplicity can be retained across CPUs GPUs in a cluster, minus frustration dealing with race conditions. Further, done unified abstraction, avoiding much complication architectures. achieved help transactional semantics...

10.1109/tpds.2016.2616314 article EN IEEE Transactions on Parallel and Distributed Systems 2016-10-11

We present a runtime system for simple and efficient programming of CPU+GPU clusters. The programmer focuses on core logic, while the undertakes task allocation, load balancing, scheduling, data transfer, etc. Our model is based shared global address space, made by transaction style bulk-synchronous semantics. This broadly targets coarse-grained parallel computation particularly suited to multi-GPU heterogeneous describe our communication scheduling report its performance ona few prototype...

10.1109/ipdps.2015.12 article EN 2015-05-01

Automatic translation validation across the unoptimized intermediate representation (IR) of original source code and optimized executable assembly is a desirable capability, has potential to compete with existing approaches verified compilation such as CompCert. A difficult subproblem automatic identification correlations transitions between two programs' respective locations. We present counterexample-guided algorithm identify these in robust scalable manner. Our both theoretical empirical...

10.1145/3428289 article EN Proceedings of the ACM on Programming Languages 2020-11-13

Peephole optimizers are typically constructed using human-written pattern matching rules, an approach that requires expertise and time, as well being less than systematic at exploiting all opportunities for optimization. We explore fully automatic construction of peephole brute force superoptimization. While the optimizations discovered by our system may be general counterparts, has potential to automatically learn a database thousands millions optimizations, in contrast hundreds found...

10.1145/1168918.1168906 article EN ACM SIGPLAN Notices 2006-10-20

Power Architecture® processors are popular and widespread on embedded systems, such platforms increasingly being used to run virtual machines. While the Architecture meets Popek-and-Goldberg virtualization requirements for traditional trap-and-emulate style virtualization, performance overhead of remains high. For example, workloads exhibiting a large amount kernel activity typically show 3-5x slowdowns over bare-metal.

10.1145/2451116.2451163 article EN 2013-03-16

Peephole optimizers are typically constructed using human-written pattern matching rules, an approach that requires expertise and time, as well being less than systematic at exploiting all opportunities for optimization. We explore fully automatic construction of peephole brute force superoptimization. While the optimizations discovered by our system may be general counterparts, has potential to automatically learn a database thousands millions optimizations, in contrast hundreds found...

10.1145/1168919.1168906 article EN ACM SIGARCH Computer Architecture News 2006-10-20

Software packet processing is increasingly commonplace, especially for software-defined networking constructs. Previous work has investigated methods to efficiently map pipelines general-purpose processor architectures. Concurrently, novel high-level domain-specific languages (DSLs) specifying modern pipeline functionality, are emerging (e.g., P4 [5]). An attractive goal develop a compiler that can automatically specification (specified in DSL) an underlying machine architecture. Ideally,...

10.1145/3124680.3124747 article EN 2017-09-02
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