A5102910830- Semiconductor materials and devices
- Chalcogenide Semiconductor Thin Films
- Advanced Thermoelectric Materials and Devices
- Advancements in Semiconductor Devices and Circuit Design
- Advanced Data Storage Technologies
- Heusler alloys: electronic and magnetic properties
- Semiconductor materials and interfaces
- Semiconductor Lasers and Optical Devices
- Advanced Memory and Neural Computing
- Ferroelectric and Negative Capacitance Devices
- Dermatologic Treatments and Research
- Electromagnetic Scattering and Analysis
- Low-power high-performance VLSI design
- Vehicle Dynamics and Control Systems
- Immune responses and vaccinations
- Skin Protection and Aging
- Autonomous Vehicle Technology and Safety
- Aerodynamics and Fluid Dynamics Research
- Polyamine Metabolism and Applications
- Telomeres, Telomerase, and Senescence
- Ocean Waves and Remote Sensing
- Phase-change materials and chalcogenides
- Dyeing and Modifying Textile Fibers
- Crystallization and Solubility Studies
- Copper Interconnects and Reliability
Shanghai Dianji University
2023-2024
East China Normal University
2024
Nanjing Foreign Language School
2023
Guangdong Pharmaceutical University
2023
Sun Yat-sen University
2022
Foshan University
2020
Texas Instruments (United States)
1986-2003
Several traditional observational studies suggested an association between COVID-19 and leukocyte telomere length (LTL), a biomarker for biological age. However, whether there was causal them remained unclear. We aimed to investigate genetically predicted is related the risk of LTL, vice versa. performed bidirectional Mendelian randomization (MR) study using summary statistics from genome-wide critically ill (n = 1 388 342) LTL 472 174) European ancestry. The random-effects inverse-variance...
With high carrier mobility and intrinsic low lattice thermal conductivity, Ag2Se compounds have attracted increasing attention for thermoelectric application near room temperature. Due to its phase transition at ∼406 K resulting volume expansion, the growth properties of large-sized single crystals seldom been reported so far. In this work, vertical Bridgeman method was used growing bulk crystal, with an orientation preference along low-symmetric (201) plane. The Hall as 2 000 cm2/(V·s) weak...
The authors describe a 256-kbit flash EEPROM (electrically erasable and programmable read-only memory) device which requires only 5 V for program, erase, read operations has performance cost comparable to that of the recently reported dual-power-supply EEPROMs, require 12 programming erase read. memory cell consists floating-gate transistor merged-pass-gate transistor. process is array-contactless (ACEE), with buried source/drain bit lines tunnel oxide module 20-V CMOS module. program employ...
Abstract Indium selenides (InSe) is a promising layer‐structured semiconductor with broad potential applications in photovoltaics, diodes, and optic devices, but its thermoelectric performance limited by the high thermal conductivity. In this work, alloying high‐performance SnSe InSe, 0.5 Sn Se crystal prepared via zone melting method. The density of measured as 5.81 g cm −3 which between pure InSe. XRD measurements indicate that grown consists InSe crystals preferred orientation along (00l)...
A revolutionary EPROM cell technology has been developed. Its suitability to realize high density memories with performance and reIiability comparable the conventional EPROMS demonstrated a 64K bit vehicle. This self-aligned contactless is in crosspoint array configuration, occupies 33 percent less area than at design rules. The planar, enhanced manufacturability, scalability ideally suited for beyond megabit density.
A 512K*8 flash EEPROM (electrically erasable programmable ROM) which operates from a single 5-V supply was designed and fabricated. double-poly, single-metal CMOS process with minimum feature size of 0.9 mu m developed to manufacture the test vehicle, resulted in die 95 mm/sup 2/. The storage cell is 8.64 m/sup 2/ consists one-transistor that uses remote, scalable, tunnel diode for programming erasing by Fowler-Nordheim tunneling. Process high-voltage requirements are relaxed utilizing...
A contactless cell array technology has been developed for a single-power-supply 5V-only CMOS flash EEPROM (electrically erasable programmable read-only memory). The technology's suitability VLSI memories demonstrated by 256-kb test vehicle. This low-current approach realized with area and cost comparable to those of the recently reported dual-power-supply EEPROMs.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
The argyrodite family has emerged as a promising thermoelectric candidate due to its highly diffusive Ag ions and inherent low thermal conductivity. To address issues that commonly arise with hot pressing (HP) sintering, this study proposes use the zone melting (ZM) method synthesize high-density polycrystalline bulk Ag8SnSe6 samples. properties of samples synthesized by ZM HP methods were thoroughly evaluated over temperature range 300 700 K. Due weaker scattering electrons, ZM-synthesized...
A full 4-Mb flash EEPROM was fabricated in 0.8-μm CMOS and its functionality verified. Conservative 1.0-μm features were used the periphery, resulting a die area of 95 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The device 5-V-only operation either full-chip or sector erase. segmented architecture, remote row decode, innovative design techniques provide erase feature high-voltage handling with improved breakdown protection isolation
A single-transistor advanced contactless EEPROM (ACEE) array technology with an 8.6 μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> cell developed for a single-power-supply 5-V only 4-Mb flash is described. This ACEE has 0.8 minimum lithographic feature sizes and novel sublithographic remote tunnel diode structure. Low-voltage isolation between bitlines of the same been achieved by at effective separation 0.65 μm; high-voltage...
Since winglet be added on the motorcycle in 2016 first, extreme speed of competition improve a lot. The engineers motorcades not only focus efficiency engine, but also put some their attention design aerodynamic kits. This paper is shape racing track to see how it effect choosing winglet. different surface area may have force provided motorcycle. finds that for which has more strait roads, should reduce drag force, so less area, vice versa. research significance help choose suitable rate and...
A CMOS contactless cell array technology has been developed for a single-power-supply high-density, five-V-only flash memory and system programmable IC applications. The technology's suitability VLSI memories demonstrated by 256-kb EEPROM (electronically erasable read-only memory) chip. This low-current approach proved, with area cost comparable to recently reported high-current dual-power-supply EEPROMs
A novel tunnel diode has been developed for high-density 5-V-only flash memories. The memory is remote from the channel, self-aligned, sublithographic, and scalable. This provides several advantages over a conventional diode: higher junction breakdown voltage, reduced substrate current during erase, oxide area, cell competitive endurance. 256-kb incorporating this shown to have excellent operation reliability characteristics.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML"...
A one megabit CMOS EPROM with a Floating gate Avalanche injection MOS (FAMOS) cell area of 8.6 µm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> has been fabricated at conservative design rule 1.2µm This cell, to our knowledge, is the smallest reported cell. The process utilized an Advanced Contactless (ACE) technology combined High Voltage Enhanced Performance Implanted (HVEPIC) technology. technique produced fully functional MBIT...