A5057933579- Advanced Memory and Neural Computing
- Ferroelectric and Negative Capacitance Devices
- Neuroscience and Neural Engineering
- Neural dynamics and brain function
- Neural Networks and Reservoir Computing
- CCD and CMOS Imaging Sensors
- Fluid Dynamics Simulations and Interactions
- Photoreceptor and optogenetics research
- Machine Learning and ELM
- Neural Networks and Applications
- EEG and Brain-Computer Interfaces
- Earthquake and Tsunami Effects
- Coastal and Marine Dynamics
- Wave and Wind Energy Systems
- Fluid Dynamics and Vibration Analysis
- 3D Surveying and Cultural Heritage
- Remote Sensing and LiDAR Applications
- 3D Shape Modeling and Analysis
Chongqing University
2020-2025
China Academy of Railway Sciences
2023
Ningbo University of Technology
2022
Human brain cortex acts as a rich inspiration source for constructing efficient artificial cognitive systems. In this paper, we investigate to incorporate multiple brain-inspired computing paradigms compact, fast and high-accuracy neuromorphic hardware implementation. We propose the TripleBrain core that tightly combines three common factors: spike-based processing plasticity, self-organizing map (SOM) mechanism reinforcement learning scheme, improve object recognition accuracy throughput,...
Spiking neural networks (SNNs) have attracted intensive attention due to the efficient event-driven computing paradigm. Among SNN training methods, ANN-to-SNN conversion is usually regarded achieve state-of-the-art recognition accuracies. However, many existing techniques impose lengthy post-conversion steps like threshold balancing and weight renormalization, compensate for inherent behavioral discrepancy between artificial spiking neurons. In addition, they require a long temporal window...
Layer-by-layer error back-propagation (BP) in deep spiking neural networks (SNN) involves complex operations and a high latency. To overcome these problems, we propose method to efficiently rapidly train SNNs, by extending the well-known single-layer Tempotron learning rule multiple SNN layers under Direct Feedback Alignment framework that directly projects output errors onto each hidden layer via fixed random feedback matrix. A trace-based optimization for is also proposed. Using such two...
For embedded, mobile and edge-computing intelligent applications, this brief proposes a low-cost real-time neuromorphic hardware system of spiking Extreme Learning Machine (ELM) equipped with on-chip triplet-based reward-modulated spike-timing-dependent plasticity (R-STDP) learning capability. Our design employs time-step pipelined dual-core architecture consisting parallel computing unit arrays to improve processing speed, as well trace-assisting mechanism on-the-fly hidden layer weight...
This brief proposes an edge neuromorphic hardware design for real-time energy-efficient applications. It is capable of fast on-chip learning on compressive sensed spikes utilizing error-triggered mechanism. Our architecture consists two event-driven arrays parallel computing cores, and adopts fine-grained pipeline circuits to boost processing speed. The has good scalability provides a flexible trade-off among speed, recognition accuracy resource cost. was prototyped the very-low-cost Xilinx...
Spiking neural networks and neuromorphic systems have attracted ever increasing interests recently, due to their high computational efficiency by imitating the functional mechanism of cerebral cortex. However, endowing low-cost chips with real-time high-accuracy on-chip learning plasticity for edge applications is still challenging. In this work, we present a digital chip multi-layer SNN in visual recognition tasks. It employs hierarchical multi-core architecture, dynamically reconfigurable...
This paper proposes a high-speed low-cost VLSI system capable of on-chip online learning for classifying address-event representation (AER) streams from dynamic vision sensor (DVS) retina chips. The proposed executes lightweight statistic algorithm based on simple binary features extracted AER and Random Ferns classifier to classify these features. system's characteristics multi-level pipelines parallel processing circuits achieves high throughput up 1 spike event per clock cycle data...
This paper presents a digital edge neuromorphic spiking neural network (SNN) processor chip for variety of intelligent cognitive applications. allows high-speed, high-accuracy and fully on-chip spike-timing-based multi-layer SNN learning. It is characteristic hierarchical multi-core architecture, event-driven processing paradigm, meta-crossbar efficient spike communication, hybrid reconfigurable parallelism. A prototype occupying an active silicon area 7.2 mm
Spiking neural networks (SNNs) and neuromorphic systems have attracted ever increasing interests recently, due to their high computational energy efficiencies originated from closely imitating the functional mechanism of cerebral cortex, which adopts sparse spikes for information processing. In this work, we present a low-cost real-time face recognition system potential edge-side intelligent applications. This is mainly built upon our prior reported MorphBungee chip, capable fast on-chip...
Due to the irregularity and complexity of ground non-ground objects, filtering data from airborne LiDAR point clouds create Digital Elevation Models (DEMs) remains a longstanding unresolved challenge. Recent advancements in deep learning have offered effective solutions for understanding three-dimensional semantic scenes. However, existing studies lack capability model global relationships fail integrate local information effectively, which are crucial cloud data, especially larger objects....
Computational efficiency is critical to many mobile and always-on face recognition applications. To this end, a heterogeneous spiking neural network (SNN) proposed for recognition. obtain high accuracy at minimal computational overheads, the SNN consists of an encoding subnet sparse image feature classification classification. The experimental results suggest that algorithm can achieve on small datasets human samples with labeled identities very low neuronal activities. promising low-cost or...
For edge intelligent applications, this work proposes a tiny neuromorphic hardware core embedding high-speed on-chip synaptic plasticity, by adopting the proposed Temporal-Integrate neuron model and simplified supervised spike-driven plasticity rule for learning. The was prototyped on very-low-cost Zybo Zynq-7010 FPGA device, attained comparably high classification accuracies many datasets (e.g. 90.4% MNIST), with learning inference speed as 11,268 11,749 f <tex...
This paper proposes a scalable, high-performance and cost-effective digital neuromorphic hardware architecture for single-layer SNN model, with fast accurate on-chip learning capability. To obtain high recognition accuracies while reducing resource cost processing latency, our combines three brain-inspired factors: the framework, self-organizing map (SOM) (i.e., unsupervised SOM-STDP rule), biological reinforcement reward-modulated STDP or R-STDP rule). Our mainly consists of parallel...
For edge intelligence applications, this work proposes a tiny spike encoding network embedded with high-speed on-chip capability, which applies the proposed dual-mode Integrate & Fire (IF) neuron model to support different coding schemes. The was prototyped on Zynq-7020 FPGA device, an speed as high 2127 frame/s, while dissipating only 69 mW under 250 MHz clock frequency. Our spiking neural hardware encoder adopts eight-core architecture for parallel computing improve processing speed,...
The spiking neural network (SNN) and event-driven neuromorphic architectures have gaining ever increasing popularity in low-cost energy-efficient edge intelligent systems, as they closely mimic the human brain mechanism by utilizing spatiotemporally sparse binary spikes to represent process sensory information neurons [1]. Especially, small-scale digital ones attract more interests for their wide deployment potential versatile edge-node applications such wearables, drones mobile platforms...