A5018078227- Semiconductor materials and devices
- Advancements in Semiconductor Devices and Circuit Design
- Ferroelectric and Negative Capacitance Devices
- Integrated Circuits and Semiconductor Failure Analysis
- Multilevel Inverters and Converters
- Advanced DC-DC Converters
- Silicon Carbide Semiconductor Technologies
- Radio Frequency Integrated Circuit Design
- Advanced Battery Technologies Research
- Induction Heating and Inverter Technology
- Semiconductor materials and interfaces
- Microgrid Control and Optimization
- 3D IC and TSV technologies
- Advancements in PLL and VCO Technologies
- Photonic and Optical Devices
China University of Mining and Technology
2023-2024
IBM (United States)
1991-2014
Infineon Technologies (United Kingdom)
2006
IBM Research - Thomas J. Watson Research Center
2004
We present a fully integrated 14nm CMOS technology featuring finFET architecture on an SOI substrate for diverse set of SoC applications including HP server microprocessors and LP ASICs. This is with 4 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sup> generation deep trench embedded DRAM to provide ultra-dense (0.0174um xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ) memory solution industry leading 'scale-out' processor design. A...
A high performance embedded DRAM with deep trench capacitor and SOI logic has been deployed in 45nm 32nm technology nodes. Following a yield ramp of the sub-2ns latency technology, we present, for first time, eDRAM fully compatible high-¿ metal gate access transistor node dielectric storage capacitor. We also describe advancements required to scale as well optimal cell retention performance. clear scaling path is seen 22nm node.
Fully silicided (FUSI), dual workfunction (WF), Ni monosilicide metal gates are demonstrated using Sb predoped polySi for setting the nFET WF and first time a combination of Al Ni(Pt) alloy silicide pFET WF. The along with Ni(Pt)Si, allow WFs spanning Si band gap to within 0.2 eV edges. With this large range FUSI, WF, NiSi process is applicable both high performance low power CMOS applications. It shown that Ni(Pt)Si have leakage currents equivalent formed from intrinsic polySi. A...
Integration of stress proximity technique (SPT) and dual liners (DSL) has been demonstrated for the first time. The liner is enhanced by spacer removal after salicidation before DSL process. It maximizes strain transfer from nitride to channel. PFET drive current improvements 20% isolated 28% nested poly gate pitch devices have achieved with SPT. Leading edge I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> =660μA/μm at...
The key result in this work is that FUSI/HfSi/sub x/O/sub y/ gate stacks offer both significant leakage reduction (due to high-/spl kappa/) and drive current improvement at T/sub inv/ /spl sim/ 2 nm to: (i) elimination of poly depletion effect, 0.5 nm, (ii) the high mobility HfSi/sub y/). We also demonstrate threshold voltage for PFETs NFETs can be adjusted from midgap values Vt(PFET)/spl -0.4 V Vt(NFET) + 0.3 by poly-Si predoping implantation (Al or As) FUSI alloying. Significantly improved...
We present an advanced CMOS integration scheme based on embedded SiGe (eSiGe) with a novel graded germanium process. The retention of channel strain enabled pFET performance gain 15% over non-graded eSiGe control. When combined compressive stress liner (CSL), the drive current reached 770muA/mum at I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</sub> = 100nA/mum V xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> 1V. Competitive nFET...
An aggressively scaled high performance 45nm bulk CMOS technology targeting graphic, gaming, wireless and digital home applications is presented. Through innovative utilization integration of advanced stressors, thermal processes other elements, at design ground rules, core NFET PFET realized world leading drive currents 1150 785 uA/um 100 nA/um off current 1V, respectively. In addition to the transistors, an ultra low-k back-end dielectric (k=2.4) significantly lowers wiring delay. this...
We present industry's smallest eDRAM cell and the densest embedded memory integrated into highest performance 32nm High-K Metal Gate (HKMG) SOI based logic technology. The is aggressively scaled at 58% (vs. 45nm) features key innovation of (HK/M) stack in Deep Trench (DT) capacitor. This has enabled 25% higher capacitance 70% lower resistance compared to conventional SiON/Poly matched leakage reliability. HKMG access transistor developed high optimized technology sub 3fA well-controlled...
The authors report on a 500-gate array implemented with AlGaAs/GaAs heterojunction bipolar transistors (HBTs) using an ECL/CML circuit approach. HBTs have f/sub t/'s and max/'s above 55 GHz. Frequency dividers personalized this gate shown flip-flop toggle rates up to 15.6 GHz, the highest ever demonstrated arrays. Measurement delay chains at 2-mA source current showed unloaded of 26 ps additional delays 8 ps/fan-out 0.12 ps/fF capacitive load. has been fabricated successfully in research...
Aiming at the optimization of current stress with low voltage ratio and full ZVS, a control method combining variable duty cycle phase shift was proposed based on dual active bridge (DAB) converters DC blocking capacitors. By adding bias to capacitors, asymmetric modulation (ADM) can adjust as needed. Based theoretical analysis steady-state operation, operating modes be divided into eight modes. According features each mode, equivalent circuits are established. The transmission power...
When the voltages of input and output ports do not match, multilevel dual active bridge (ML-DAB) exists problems large root mean square (RMS) current. A novel promising modulation, called Asymmetric duty modulation (ADM), provides an approach different from conventional scheme to improve performance DAB converter. Based on it, a hybrid is proposed in this article reduce rms current inductor. Firstly, operational principle has been introduced. Then transmission power calculated inductor...
This paper presents a cost-effective low power 45nm bulk technology platform, primarily designed to serve the wireless multimedia and consumer electronics need. platform features carbon co-IIP in nMOS halo, laser annealing scheme, stress liner on 45°-rotated wafer (〈100〉) for process simplicity achieve high device performance leakage together. Drive current as 650/320 uA/um at Ioff of 0.5 nA/um with Vdd=1.1V has been achieved both NMOS PMOS respectively. Ring oscillator speed (FO=1) boosted...
In this paper, we describe the unique scaling challenges, critical sources of variation, and potential trench leakage mechanisms 32nm capacitors that utilize high-κ/metal electrode materials. This is first eDRAM technology has successfully integrated high-κ metal films as part capacitor. addition, these are found to be fully compatible with front-end line (FEOL) thermal budgets. We explore variation illustrate process mitigation techniques, including targeting key capacitor properties,...
A novel low cost technique to improve device performance by enhanced Stress Proximity Technique (eSPT) with Recessed S/D (ReSD) has been demonstrated for the first time. pFET improvement of 40% was eSPT. Ion 520uA/um at Ioff 1nA/um achieved processes. With optimized eSPT, 15% in ring delay demonstrated.
To further improve the optimization of a dual active bridge (DAB) converter and enhance efficiency., hybrid mode optimal asymmetric duty modulation scheme based on DC blocking capacitors for optimizing root-mean-square (RMS) value fundamental component inductor current has been proposed. By capacitors., operation is divided into two modes. universal high-frequency-link model, transmission power RMS under each are derived. This strategy takes as target, with constraint, utilizes numerical...
For nFET, mechanism of Stress Memorization Technique (SMT) has been investigated. It showed, for the first time, that SMT effect on nFET improvement is not only from poly gate, but also Si at extension area. pFET, a novel low cost technique to improve device performance by enhanced Proximity (eSPT) with Recessed SD (ReSD) demonstrated time. pFET 40% was eSPT. 15% in ring delay optimized
The integration of 3 major techniques process induced stress, stress memory technique (SMT), dual liners (DSL), and proximity (SPT), has been demonstrate for advanced CMOS technology. device performance improvement from each their addability are discussed