A5051733717- Advancements in Semiconductor Devices and Circuit Design
- Semiconductor materials and devices
- Radio Frequency Integrated Circuit Design
- Microwave Engineering and Waveguides
- Integrated Circuits and Semiconductor Failure Analysis
- Advanced Memory and Neural Computing
- Semiconductor Quantum Structures and Devices
- Quantum Dots Synthesis And Properties
- Ferroelectric and Negative Capacitance Devices
- Silicon Carbide Semiconductor Technologies
- Luminescence Properties of Advanced Materials
- Acoustic Wave Resonator Technologies
- Low-power high-performance VLSI design
- Analog and Mixed-Signal Circuit Design
- Electromagnetic Compatibility and Noise Suppression
- Energy Harvesting in Wireless Networks
- Advanced Power Amplifier Design
- Advancements in PLL and VCO Technologies
- Appendicitis Diagnosis and Management
- Photovoltaic System Optimization Techniques
- Radiation Effects in Electronics
- Terahertz technology and applications
- Semiconductor Lasers and Optical Devices
- Thin-Film Transistor Technologies
- Cryptographic Implementations and Security
Hangzhou First People's Hospital
2024
Westlake University
2024
Hua Hong Semiconductor (China)
2022
Hanyang University
2021
Taiwan Semiconductor Manufacturing Company (China)
2009-2019
Grace (United States)
2017
IBM (United States)
2006-2014
Institute of Microelectronics
2014
Chinese Academy of Sciences
2014
National Center for Advanced Packaging (China)
2014
We present a fully-integrated SOI CMOS 22nm technology for diverse array of high-performance applications including server microprocessors, memory controllers and ASICs. A pre-doped substrate enables scaling this third generation deep-trench-based embedded DRAM dense hierarchy. Dual-Embedded stressor SiGe Si:C improved carrier mobility in both PMOS NMOS FETs is presented the first time. hierarchical BEOL with 15 levels copper interconnect self-aligned via processing delivers high performance...
A high performance embedded DRAM with deep trench capacitor and SOI logic has been deployed in 45nm 32nm technology nodes. Following a yield ramp of the sub-2ns latency technology, we present, for first time, eDRAM fully compatible high-¿ metal gate access transistor node dielectric storage capacitor. We also describe advancements required to scale as well optimal cell retention performance. clear scaling path is seen 22nm node.
This Letter proposes a low‐cost, single event double‐upset tolerant latch which utilises interlocked nodes to keep data, clock gating (CG) in Muller C‐element (MCE) turn off the storage cell, three‐input MCE block soft error from cell and weak keeper prevent high impedance state. The proposed has better reliability than conventional triple path dual‐interlocked (TPDICE). Most up‐to‐date (SEDU) latches are carried out with too large cost penalties. one saves up 93.32% area‐power‐delay product...
In this paper, we investigate the retention time distribution of IBM's 65nm node embedded DRAM. We demonstrate that subthreshold current is dominant leakage mechanism determines data time, and can be attributed to array V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t</sub> variation. Based on study, present a new technique for characterization across-chip The median value standard deviation transfer devices within an eDRAM are estimated by...
A 0.5-V low noise amplifier (LNA) for 2.4 GHz medical application based on 0.18 μm CMOS process is presented in this paper. To achieve and high gain with the constraint of voltage power consumption, a novel modified complementary current-reused LNA using forward body bias technology proposed. diode connected MOSFET technique employed to minimize leakage improve performance. notch filter isolator harmonic rejection constructed linearity voltage. The measured results show that proposed...
In this work, a new type of flash memory-based memristor, named programmable linear random-access memory (PLRAM), is presented to store analog synaptic weights in single cell. A PLRAM cell with self-calibrating program/erase scheme can provide very stable and repeatable states up 7 bits cell, which suitable for an artificial synapse the neural network. The physical implementation discrete Fourier transform on arrays shows remarkably good agreement theoretical calculations. By taking...
We present industry's smallest eDRAM cell and the densest embedded memory integrated into highest performance 32nm High-K Metal Gate (HKMG) SOI based logic technology. The is aggressively scaled at 58% (vs. 45nm) features key innovation of (HK/M) stack in Deep Trench (DT) capacitor. This has enabled 25% higher capacitance 70% lower resistance compared to conventional SiON/Poly matched leakage reliability. HKMG access transistor developed high optimized technology sub 3fA well-controlled...
Summary A duplex current‐reused complementary metal–oxide–semiconductor low‐noise amplifier (LNA) is proposed for 2.5‐GHz application. The topology with equivalent three common‐source gain stages cascaded utilized to fulfil the low‐power consumption and high simultaneously. derivative superposition linearization technique bulk‐bias control employed improve linearity performance large‐signal swing extend auxiliary transistors bias‐control range. LNA fabricated in a 0.18‐um 1P5M process...
Shallow Trench Isolation (STI) and Stepped Oxide (SO) -based N-type LDMOS are simultaneously studied for the first time low-voltage power device in this paper. Ultra-low specific on-resistance (Rsp) can be obtained both STI- SO-based by scaling channel length (LCH) as well using optimized drift implant. It was indicated that, to some extent, LCH effectively reduces Rsp without sacrificing breakdown voltage (BV). This is mainly ascribed enhanced conducting capability of shorter cell pitch....
Mechanical stress-enhanced plasma process-induced damage (PPID) in 0.13-mum pMOSFET was investigated. The PPID, which initially charged neutral, became positively during hydrogen annealing, thus, changing the PMOS threshold voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> ). Different device structures were designed to evaluate mechanical stress effects on PPID. features of these positive charges, including PPID induced V...
A highly reliable 2-bits/cell split-gate flash memory cell in a novel program-disturbs immune array architecture is fabricated and demonstrated. Using metal interconnect technique, new virtual-ground realized to greatly improve program disturbs as compared with conventional and-type configuration. fully self-aligned process shallow trench isolation also proposed for the first time fabricate this word-line shared structure without any lithomisalignment issue. Moreover, negative charge trap...
A 2.5-GHz low power high gain and linearity CMOS noise amplifier (LNA) is presented. The modified derivative superposition (MDS) technique employed to improve the performance. bulk-bias control of auxiliary transistor (AT) in MDS used extend AT's bias range. current-reused topology utilized full-fill consumption simultaneously. proposed LNA fabricated a 0.18-μm 1P3M RF process consumes 4.36-mA quiescent current from 1V voltage supply. measurement results show that achieves 20.1dB gain,...
ABSTRACT This article presents the design of a 2.4 GHz low power high gain and linearity current‐reused CMOS noise amplifier (LNA) using modified derivative superposition (MDS) technique with bulk‐bias control. The MDS control is used to extend auxiliary transistor's bias range enhance performance. topology utilized fulfill consumption gain, simultaneously. proposed LNA fabricated in 0.18‐μm 1P6M SiGe BiCMOS process consumes 6.53 mA quiescent current from 1 V voltage supply. measurement...
We present a 65nm embedded DRAM cell (0.127 μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> Cell size) on unpatterned SOI fabricated using standard high performance technology with dual stress liner (DSL) (1). The utilizes low-leakage 2.2-nm gate oxide pass transistor and deep trench capacitor. A side wall spacer process enables simplified collarless process. Connection to the buried plate is realized by silicided substrate guardrings...
A 200-KB embedded electrically erasable programmable READ-only memory (EEPROM), which operates with a single 1.5-V power supply voltage based on an HHGRACE (Shanghai Huahong Grace Semiconductor Manufacturing Corporation) 90-nm EEPROM process, is developed. In this brief, several key design techniques are presented. An improved bit cell larger current sensing window adopted in the split-source array. To get high-speed READ operation, high-performance sense amplifier and dynamic tracking...
We propose a novel computer architectural concept of instruction overloading to support block ciphers. Instead adding new instructions, we extend only the execution some existing instructions. The proposed method allows central processing unit core execute different operations for same depending on address data, similar operator in object-oriented languages. first present an extension AES algorithm, then demonstrate its enhanced applicability with two further extensions supporting multiple...
A laterally double-diffused metal-oxide-semiconductor (LDMOS) field-effect transistor with stepped filed plates (SFP) from 12V to 40V was proposed in this work. scheme of multi field were obtain better comprehensive performance. Furthermore, two oxides (SO) has been achieved and fabricated only one additional mask for 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">nd</sup> SO. With SFP, the trenched current flow path can be removed....
Emission of bright (over 9 cd/m2) violet light centered at 404 nm has been achieved from SrS:Eu thin-film electroluminescent (EL) devices. The brightness remained stable after several hours operation. source this is believed to be the 5d–4f transition Eu2+ in SrCl2 host, which formed near ZnS/SrS interfaces within sandwich structure EL Similar device structures were also utilized produce ultraviolet emission 367 SrCl2:Ce3+ layers. These devices grown via atomic layer epitaxy.
A 0.35μm 600V ultra-thin epitaxial BCD technology for high voltage gate driver IC is developed in this work, including LDMOS, isolation ring, asymmetric 20V NMOS, PMOS, symmetric PMOS and BJT. Only 15 photo layers are used the proposed 1P2M technology. The experimental devices demonstrate that BVs of divided RESURF structures 770V, between V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</sub> LDMOS side...
Fabrication of green light emitting ZnS:Tb thin film electroluminescent devices using atomic layer epitaxy is described. In this investigation, particular emphasis placed on the effect Tb doping profiles and concentrations emission characteristics. It shown that rapid thermal anneal these has a significant their lifetimes.
RFFE module design for 5G is integrated with cost effective in 0.13um RFSOI CMOS technology. Design of high power antenna switch SP12T achieves IL<;1dB and worst case isolation>21dB at Sub-6GHz maximum handling capacity, Pmax>36dBm harmonic distortion <;-45dBm 1mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> chip area. PAC the tuning ratio >20 Q>45 1GHz realized impedance aperture tuning. A 6-Bit attenuator digital attenuation step...