A5101787974- Radio Frequency Integrated Circuit Design
- Radiation Effects in Electronics
- Microwave Engineering and Waveguides
- VLSI and Analog Circuit Testing
- Semiconductor materials and devices
- Advanced Power Amplifier Design
- Advanced DC-DC Converters
- Superconducting and THz Device Technology
- Energy Harvesting in Wireless Networks
- PAPR reduction in OFDM
- Electromagnetic Compatibility and Noise Suppression
- Advanced Memory and Neural Computing
- Advancements in Semiconductor Devices and Circuit Design
- Low-power high-performance VLSI design
- Distributed systems and fault tolerance
University of Chinese Academy of Sciences
2018-2021
Shanghai Institute of Microsystem and Information Technology
2018-2021
Chinese Academy of Sciences
2018-2019
Taiwan Semiconductor Manufacturing Company (China)
2018
Innosys (United States)
2005
With the CMOS technology scaling down, normal latch is more susceptible to soft errors caused by radiation particles. In this paper, we proposed a low-power and highly reliable hardened enhance single event upset (SEU) tolerance. Based on DICE Muller C-element circuit, can provide 100% fault tolerance, which be used for space applications in severe ray environments. The simulation show that's it not only completely tolerate an SEU any one of its internal node, but also double-node...
This Letter proposes a low‐cost, single event double‐upset tolerant latch which utilises interlocked nodes to keep data, clock gating (CG) in Muller C‐element (MCE) turn off the storage cell, three‐input MCE block soft error from cell and weak keeper prevent high impedance state. The proposed has better reliability than conventional triple path dual‐interlocked (TPDICE). Most up‐to‐date (SEDU) latches are carried out with too large cost penalties. one saves up 93.32% area‐power‐delay product...
In this paper, an improved design of a radiation hardened memory cell (RHMC), based on the SEU (single event upset) physics mechanism and reasonable transistor size, is proposed.The can enhance reliability for space environment, which also offer differential read operation robust sensing.With help 90 nm standard digital CMOS technology, simulation demonstrates that proposed has ability to recover in any one sensitive node provides multiple-node upsets protection.The comparisons previous...
RFFE module design for 5G is integrated with cost effective in 0.13um RFSOI CMOS technology. Design of high power antenna switch SP12T achieves IL<;1dB and worst case isolation>21dB at Sub-6GHz maximum handling capacity, Pmax>36dBm harmonic distortion <;-45dBm 1mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> chip area. PAC the tuning ratio >20 Q>45 1GHz realized impedance aperture tuning. A 6-Bit attenuator digital attenuation step...
A novel stacked class-E-like power amplifier (PA) topology with dual drain output technique is proposed in this paper. Owing to the enhanced technique, total 1.25 times of conventional class-E PA single output. Meanwhile, benefited from low ON resistance switch device on high and trap-rich substrate RFSOI technology, PAE cost performance are also obtained. In particular, a differential an on-chip transformer based combiner has been implemented 0.18 um radio frequency silicon-on-insulator...
Abstract This paper presents a theoretical analysis for achieving uniform voltage distribution among stacked field effect transistors (FETs) of RF tuner switch. The peak ( V ) is limited by the unequal divided drop FETs. A simplified equivalent capacitor circuit established and an analytical expression then derived first time to decide value ideal capacitance each FET in stack equal division. Varying size set that drain‐to‐source C ds equals from proposed can obtain distribution, thus much...
In this paper, an improved SEU hardened SRAM bit-cell, based on the physics mechanism and reasonable circuit-design, is proposed. The simulation results show that cell can provide full immunity for single node upset multiple-node upset. Besides, it suitable low-power application.
Abstract This work presents both high power and linearity CMOS cascode amplifier (PA) with adaptive dynamic bias (ADB) circuit. The ADB circuit sets appropriate gate for the common source (CG) amplifiers according to input envelope signal, significantly improving linearity. Meanwhile, harmonic termination circuits are introduced at of CG center‐tap node output transformer short second component ground, further In addition, this utilizes an on‐chip series‐connected transformer‐based combiner...
A wideband frequency doubler used in a satellite modulator for DVB-RCS (DVB return channel via satellite) applications is presented. The based on regeneration configuration and fabricated 0.35/spl mu/m SiGe process. exhibits large output signal swing very low phase noise degradation with an bandwidth of 4.1GHz.