S.-Z. Yao

ORCID: 0009-0008-0524-5724
Publications
Citations
Views
---
Saved
---
About
Contact & Profiles
Research Areas
  • VLSI and FPGA Design Techniques
  • VLSI and Analog Circuit Testing
  • Advancements in Photolithography Techniques
  • Optimization and Packing Problems
  • Manufacturing Process and Optimization
  • Embedded Systems Design Techniques
  • Algorithms and Data Compression
  • 3D IC and TSV technologies
  • Computational Geometry and Mesh Generation
  • Software Testing and Debugging Techniques
  • Advanced Manufacturing and Logistics Optimization

Yantai University
2025

Guangdong University of Technology
2024

University of California, San Diego
1991-2002

Cadence Design Systems (United States)
1991

Multiview data, characterized by rich features, are crucial in many machine learning applications. However, effectively extracting intraview features and integrating interview information present significant challenges multiview (MVL). Traditional deep network-based approaches often involve multiple layers to derive latent. In these methods, the of different classes typically implicitly embedded rather than systematically organized. This lack structure makes it challenging explicitly map...

10.1109/tnnls.2025.3546660 article EN IEEE Transactions on Neural Networks and Learning Systems 2025-01-01

In industry, cutting various irregular pieces from a large raw material plate of given size is often necessary to minimize the number sheets used. This problem known as two-dimensional bin packing (2DIBPP). An iterative compression algorithm proposed address in sheet metal considering lead lines maximize utilization. Firstly, three methods pre-processing are effectively transform constraints into non-overlapping between pieces. Secondly, an improved greedy heuristic, incorporating...

10.1109/access.2024.3437729 article EN cc-by-nc-nd IEEE Access 2024-01-01

In the layout stage of VLSI and printed circuit board (PCB) design, after all modules (rectangular) are placed, it is possible to flip so as reduce total net length. The authors formulate orientation a graph problem prove be NP-complete. shown equivalent finding minimum cut with some arcs negative capacities. many cases, can decomposed into subgraphs search space for optimum orientation. Experiments real cases show that module reduces length improves routability.< <ETX...

10.1109/12.90255 article EN IEEE Transactions on Computers 1991-06-01

The compaction of IC layouts subjected to conditional spacing rules in multiple-level metal technology is addressed. constraints imposed by make the automatic layout much more difficult than when usual minimum separation are applied. To solve problem, each rule formulated with a set arcs constraint graph representation. It proven that finding optimal solution under one bridge NP-complete. A graph-theory method which, reducing problem size, can efficiently obtain an proposed.< <ETX...

10.1109/43.125095 article EN IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 1992-04-01

Discusses substrate short/open fault detection in MCM manufacturing, and propose a complete open coverage algorithm which generates minimum number of tests required to completely cover all faults. The only about half the test size compared that ordinary approaches. Multi-dimensional TSP algorithms are devised optimize probe routes with quite encouraging results.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

10.1109/asic.1991.242925 article EN 2002-12-09

After all (rectangular) circuit modules are placed, it may still be possible to flip the so as reduce total net length. The orientation of is formulated a graph problem and proved NP-complete. shown equivalent finding minimum cut with some arcs negative capacities. In many cases, decompose into subgraphs search space for optimum orientation. Experiments real cases show that an reduces length improves routability.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML"...

10.1109/iscas.1990.112442 article EN 1993 IEEE International Symposium on Circuits and Systems 2002-12-04

The authors attempt to find a compaction algorithm that can suitably handle conditional constraints, such the area of compacted layout be smaller than made by traditional compactors. While has many potential applications, focus is on its application multiple-layer routings. constraints imposed make automatic much more difficult when usual minimum separation are applied. To solve problem, first formulate each spacing constraint with set arcs in graph representation. It proven finding optimal...

10.1109/iscas.1991.176706 article EN 2022 IEEE International Symposium on Circuits and Systems (ISCAS) 1991-01-01
Coming Soon ...