A5035435609- Low-power high-performance VLSI design
- Error Correcting Code Techniques
- VLSI and FPGA Design Techniques
- Coding theory and cryptography
- Cryptographic Implementations and Security
- Embedded Systems Design Techniques
- VLSI and Analog Circuit Testing
- Cryptography and Data Security
- Advanced Wireless Communication Techniques
- Cryptography and Residue Arithmetic
- Chaos-based Image/Signal Encryption
- Neural dynamics and brain function
- Advanced Memory and Neural Computing
- Parallel Computing and Optimization Techniques
- Interconnection Networks and Systems
- Physical Unclonable Functions (PUFs) and Hardware Security
- Systemic Lupus Erythematosus Research
- Ferroelectric and Negative Capacitance Devices
Intel (United States)
2014
Fulcrum Corporation (United States)
2011
University of Southern California
2007
Trellis Bioscience (United States)
2005
Loihi is a 60-mm2 chip fabricated in Intels 14-nm process that advances the state-of-the-art modeling of spiking neural networks silicon. It integrates wide range novel features for field, such as hierarchical connectivity, dendritic compartments, synaptic delays, and, most importantly, programmable learning rules. Running convolutional form Locally Competitive Algorithm, can solve LASSO optimization problems with over three orders magnitude superior energy-delay-product compared to...
Editors' note:The high-performance benefits of asynchronous design have hitherto been obtained only using full-custom design. This article presents an industrial-strength ASIC CAD flow that enables the automatic synthesis and physical high-level specifications into GHz silicon, greatly reducing time enabling far wider use technology.—Montek Singh (UNC Chapel Hill) Luciano Lavagno (Politecnico di Torino)
Fully Homomorphic Encryption (FHE) allows for secure computation on encrypted data. Unfortunately, huge memory size, computational cost and bandwidth requirements limit its practicality. We present BASALISC, an architecture family of hardware accelerators that aims to substantially accelerate FHE computations in the cloud. BASALISC is first implement BGV scheme with fully-packed bootstrapping – noise removal capability necessary arbitrary-depth computation. It supports a customized version...
Modern turbo-like codes (TLCs), including concatenated convolutional and low density parity check (LDPC) codes, have been shown to approach the Shannon limit on additive white Gaussian noise (AWGN) channel Many design aspects remain relatively unexplored, however, TLC for maximum flexibility, very error rate performance, amenability simple or high-speed hardware codecs. In this paper we address these issues by suggesting a new class of TLCs that call systematic with serially (S-SCP) codes....
The design of a commercially-shipping 72-port 10G Ethernet switch router integrated circuit is presented. 1.2 billion transistor chip consists core > 1GHz asynchronous circuits surrounded by standard synchronous logic for external interfaces. It manufactured in TSMC 65nm process. circuitry includes 15MB single-ported SRAM, 150KB dual-ported 100KB TCAM, Tb bandwidth crossbars, and fully pipelined programmable packet processor processing one packets per second. implementation relied heavily on...
This paper explores the advantages of high performance asynchronous circuits in a semi-custom standard cell environment for high-throughput turbo coding. Turbo codes are high-performance error correction used applications where maximal information transfer is needed over limited-bandwidth communication link presence data corrupting noise. Specifically we designed an high-speed decoder that can be potentially new wireless communications protocols with close to OC-12 throughputs. The design...
Fully Homomorphic Encryption (FHE) allows for secure computation on encrypted data. Unfortunately, huge memory size, computational cost and bandwidth requirements limit its practicality. We present BASALISC, an architecture family of hardware accelerators that aims to substantially accelerate FHE computations in the cloud. BASALISC is first implement BGV scheme with fully-packed bootstrapping -- noise removal capability necessary arbitrary-depth computation. It supports a customized version...
This paper proposes the method of generating asynchronous circuits from hardware description language specifications by clustering synthesized gates into pipeline stages while preserving liveness, meeting throughput and latency constraints, minimizing area. provides a form automatic pipelining in which overall design is not limited to clock frequency or level original Register-Transfer Level (RTL) specification. The design-style agnostic thus applicable many styles.
In this paper, we describe and analyze an island-based random dynamic voltage scaling (iRDVS) approach to thwart power side-channel attacks. We first the impact of number independent islands on resulting signal-to-noise ratio trace misalignment. As part our analysis misalignment, propose a novel unsupervised machine learning (ML) based attack that is effective systems with three or fewer voltages. Our results show iRDVS four islands, however, cannot be broken 200k encryption traces,...
Tree-structured soft-in/soft-out (SISO) processors provide an exponential speed-up relative to the standard forward-backward algorithm (FBA). These tree-SISOs were originally described analogously fast tree-structured adders and later as message-passing on a binary tree graphical model for finite state machine (FSM). In this paper, we summarize unify these theoretical results also recent efforts implement high-speed iterative decoders based tree-SISOs. Specifically, design tree-SISO...