This paper presents a dynamic bit-width adaptation scheme for applications using discrete cosine transform (DCT). The technique can efficiently trade off image quality and computation energy. Based on sensitivity differences of 64 DCT coefficients, separate operand bit-widths are used different frequency components to reduce To select the appropriate that achieve significant reduction power consumption with minimum degradation, we also propose selection algorithm. proposed variable bit...

Designing high-performance systems with high yield under parameter variations has raised serious design challenges in nanometer technologies. In this paper, we propose a profit-aware model, based on which present statistical methodology to improve profit of considering frequency binning and product price profile. A low-complexity sensitivity-based gate sizing algorithm is developed the profitability over an initial yield-optimized design. We also determine optimal bin boundaries for...

In this paper, we present a novel finite-impulse response (FIR) filter synthesis technique that allows for aggressive voltage scaling by exploiting the fact all coefficients are not equally important to obtain ldquoreasonably accuraterdquo response. Our implements level-constrained common-subexpression-elimination algorithm, where can constrain number of adder levels (ALs) required compute each coefficient outputs. By specifying tighter constraint (in terms adders in critical path) on...

This study was carried out to investigate the protective effects of hot-water extract from Artemisia iwayomogi (Compositae) on carbon tetrachloride-induced liver fibrosis in rats. Liver injury induced by oral administration tetrachloride (1 mL kg(-1)) twice a week during 4 weeks A. treatment. Extracts were prepared and administered rats orally (2 g kg(-1) as for weeks) follows: group 1, extract; 2, ethanol-soluble part 3, ethanol-insoluble 4, methanol extract. In treated with extract,...

With technology scaling, devices are increasingly prone to process variations. These variations cause a large spread in leakage power, since it is extremely sensitive variations, which turn results larger temperature across different dies. In this paper, we investigate the FinFET circuits considering following parameters (i) channel length and (ii) body thickness. We estimate variation under fluctuation by Monte Carlo simulation with thermal models solve power self-consistently. The show...

In this work we propose a methodology to self-consistently solve leakage power with temperature predict thermal runaway. We target 28n m FinFET based circuits as they are more prone runaway compared bulk-MOSFETs. generate models for logic cells determine the map of circuit block. Our proposed condition shows design trade off between primary input (PI) activity block, sub-threshold at room and resistance package. show that in circuits, can occur ITRS specified (150nA/μm, highperformance)...

In this paper, a profit-aware design metric is proposed to consider the overall merit of in terms power and performance. A statistical methodology then developed improve economic considering frequency binning product price profile. low-complexity sensitivity-based gate sizing algorithm gain over its initial yield-optimized design. Finally, we present an integrated for simultaneous bin boundary determination enhance profit under area constraint. Experiments on set ISCAS'85 benchmarks show...

In this paper, we propose a methodology to solve leakage power self-consistently with temperature predict thermal runaway. We target 28-nm-technology-node FinFET-based circuits as they are more prone runaway because of self-heating and less efficient heat dissipation compared bulk metal-oxide-semiconductor field-effect transistors. have generated models for logic cells-inverter, NAND, NOR-to determine the map circuit block. Our cell-level account lateral flow (contribution neighboring cells)...

Designing high-performance systems with high yield under parameter variations has raised serious design challenges in nanometer technologies. In this paper, we propose a profit-aware model, based on which present statistical methodology to improve profit of considering frequency binning and product price profile. A low-complexity sensitivity-based gate sizing algorithm is developed the profitability over an initial yield-optimized design. We also determine optimal bin boundaries for...

With technology scaling, elevated temperatures caused by increased power density create a critical bottleneck modulating the circuit operation. advent of FinFET technologies, cooling is becoming bigger challenge because thick buried oxide inhibiting heat flow to sink and confined ultra-thin channel increasing thermal resistivity. In this work, we propose compact models predict temperature rise in structures. We develop cell-level for standard INV, NAND NOR gates accounting transfer across...

In this work, we propose a methodology to self-consistently solve leakage power with temperature predict thermal runaway. We target 28nm FinFET based circuits as they are more prone runaway compared bulk-MOSFETs. generate models for logic cells determine the map of circuit block. Our proposed condition shows design trade off between primary input (PI) activity block, sub-threshold at room and resistance package. show that in circuits, can occur ITRS specified (150nA/mum, high-performance)...

In this paper, we present a novel FIR filter synthesis technique that allows aggressive voltage scaling by exploiting the fact all coefficients are not equally important to obtain "reasonably accurate" response. Our implements Level Constrained Common Subexpression Elimination (LCCSE) algorithm, where can constrain number of adder levels required compute each coefficient outputs. By specifying tighter constraint (in terms adders in critical path) on coefficients, ensure later computational...

With technology scaling, devices are increasingly prone to process variations. These variations cause a large spread in leakage power, since it is extremely sensitive variations, which turn results larger temperature across different dies. In this paper, we investigate the FinFET circuits considering following parameters (i) channel length and (ii) body thickness. We estimate variation under fluctuation by Monte Carlo simulation with thermal models solve power self-consistently. The show...

In pervasive computing environments, where various types of information are publicly owned, and multiple users access the networks via networked devices anytime anywhere, control that grants permission to an authorized user is definitely needed for secure access. Context awareness refers idea computers can both sense react based on context in their environments. many schemes, recently, has been utilized guarantee dynamic according current schemes utilizing have proposed. However, previous...

Power dissipation and robustness to process variation have conflicting design requirements. Scaling of voltage is associated with larger variations, while Vdd upscaling or transistor up-sizing for parametric-delay tolerance can be detrimental power dissipation. However, a class signal-processing systems, effective tradeoff achieved between scaling, tolerance, ldquooutput quality.rdquo In this paper, we develop novel low-power variation-tolerant algorithm/architecture color interpolation that...

Abstract Background Recently, there are growing needs of immune modulators that can convert cold tumors into hot tumors, which be utilized for combination treatment with existing related therapies. An orally available small molecule is capable activating innate response an ideal candidate to meet those needs. Upon binding 2’3’-cGAMP, STING activates TBK1-IRF3 signaling cascade in cancer cells as well host and promotes responses against cells, leading T cell mediated anti-tumor immunity by...

We present a dynamic bit-width adaptation scheme in DCT applications for efficient trade-off between image quality and computation energy. Based on sensitivity differences of 64 coefficients, various operand bit-widths are used different frequency components to reduce energy operation. Numerical results show that our architecture can achieve power savings ranging from 36% 75% compared normal

During the last two decades, self-heating has become a significant bottleneck to continued scaling of microelectronics. This is particular problem in emerging finFET designs because use thick buried oxide layers which impede heat flow sink. A possible solution architectural and circuit-level techniques make temperature field as uniform on chip. These require prediction at level 100s-1000s transistors, must relate predicted activity devices. In this paper, compact thermal models circuit...

This paper presents a stage-level clock-gating scheme for clock power improvement. The proposed technique efficiently implements the concept of transparent pipeline which improves clocking by dynamically making registers transparent. We developed new control can be applied to any number stages. A low-overhead flip-flop with mode is also reduce implementation overhead. logic extended collapsing allows energy/performance trade-off through dynamic frequency scaling. Simulation results on IBM 90...

Self-acting air bearings are increasingly used in supporting small high-speed rotating bodies. In this study we report on the effects of design parameters axial stiffness spiral-grooved various curvatures. The selected include fundamental clearance, groove depth, and bearing number. Coordinate transformation is performed to deal effectively with pressure distribution at gap between stator rotor obtained numerically, load calculated from results.

With technology scaling, elevated temperatures caused by increased power density create a critical bottleneck modulating the circuit operation. advent of FinFET technologies, cooling is becoming bigger challenge because thick buried oxide inhibiting heat flow to sink and confined ultra-thin channel increasing thermal resistivity. In this work, we propose compact models predict temperature rise in structures. We develop cell-level for standard INV, NAND NOR gates accounting transfer across...

This paper presents a stage-level clock-gating scheme for clock power improvement. The proposed technique efficiently implements the concept of transparent pipeline which improves clocking by dynamically making registers transparent. We developed new control can be applied to any number stages. A low-overhead flip-flop with mode is also reduce implementation overhead. logic extended collapsing allows energy/performance trade-off through dynamic frequency scaling. Simulation results on IBM...