FPGA with Improved Routability and Robustness in 130nm CMOS with Open-Source CAD Targetability

• DOI: 10.48550/arxiv.1712.03411
• Publication Date: 2017-01-01
• Authors: Guanshun Yu; Tom Y. Cheng; Blayne Kettlewell; Harrison Liew; Mingoo Seok; Peter R. Kinget
• Keywords: Verilog; Robustness; Bitstream; FPGA prototype; Schematic; Electronic design automation

This paper outlines an FPGA VLSI design methodology that was used to realize a fully functioning chip in 130nm CMOS with improved routability and memory robustness. The architectural space exploration synthesis capability were enabled by the Verilog-to-Routing CAD tool. capabilities of this tool extended enable bitstream generation deployment. To validate architecture implementation, Chisel (Constructing Hardware Embedded Scala Language) model created rapidly verify microarchitectural details device prior schematic design. A custom carrier board configuration correct operational characteristics over various resource utilizations clock frequencies.