BetterV: Controlled Verilog Generation with Discriminative Guidance

• DOI: 10.48550/arxiv.2402.03375
• Publication Date: 2024-02-03
• Authors: Z. F. Pei; Hui‐Ling Zhen; Mingxuan Yuan; Yu Huang; Bei Yu
• Keywords: Discriminative model; Verilog

Due to the growing complexity of modern Integrated Circuits (ICs), there is a need for automated circuit design methods. Recent years have seen rising research in hardware language generation facilitate process. In this work, we propose Verilog framework, BetterV, which fine-tunes large models (LLMs) on processed domain-specific datasets and incorporates generative discriminators guidance particular demands. The modules are collected, filtered from internet form clean abundant dataset. Instruct-tuning methods specially designed fine-tuned LLMs understand knowledge about Verilog. Furthermore, data augmented enrich training set also used train discriminator downstream task, leads optimize implementation. BetterV has ability generate syntactically functionally correct Verilog, can outperform GPT-4 VerilogEval-machine benchmark. With help task-specific discriminator, achieve remarkable improvement various electronic automation (EDA) tasks, including netlist node reduction synthesis verification runtime with Boolean Satisfiability (SAT) solving.