We present electrical characterization of GaSb/InAs(Sb) nanowire tunnel field-effect transistors. The broken band alignment the heterostructure is exploited to allow for interband tunneling without a barrier, leading high on-current levels. report maximum drive current 310 μA/μm at <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">VDS</i> = 0.5 V. Devices with scaled gate oxides display transconductances up...

Tunneling field-effect transistors (TunnelFET), a leading steep-slope transistor candidate, is still plagued by defect response, and there large discrepancy between measured simulated device performance. In this work, highly scaled InAs/InxGa1-xAsySb1-y/GaSb vertical nanowire TunnelFET with ability to operate well below 60 mV/decade at technically relevant currents are fabricated characterized. The structure, composition, strain characterized using transmission electron microscopy emphasis...

An n-type InAs/InAsP heterostructure nanowire field-effect transistor has been fabricated and compared with a homogeneous InAs transistor. For the same device geometry, by introduction of heterostructure, threshold voltage is shifted 4 V, maximum current on-off ratio enhanced factor 10 000, subthreshold swing lowered to At time, drive remains constant for fixed gate overdrive. A single transconductance 5 μA/V at low source−drain 0.3 V. transistor, we deduced high electron mobility 1500 cm2/Vs.

In this letter we report on high-frequency measurements vertically standing III−V nanowire wrap-gate MOSFETs (metal−oxide−semiconductor field-effect transistors). The transistors are fabricated from InAs nanowires that epitaxially grown a semi-insulating InP substrate. All three terminals of the defined by wrap around contacts. This makes it possible to perform vertical MOSFETs. We present S-parameter performed matrix consisting 70 MOSFETs, which have gate length about 100 nm. highest unity...

In this paper, we report on the development of a vertical wrap-gated field-effect transistor based epitaxially grown InAs nanowires. We discuss some important steps involved in growth and processing, such as nanowire position control, situ doping, high- kappa dielectric deposition, spacer layer formation, metal wrap-gate fabrication. particular, compare few alternative methods for deposition materials onto structures their potential advantages limitations. Finally, also present comparison...

Semiconductor nanowires have attracted considerable attention during the last decade and are considered as an alternative path to extend road for scaled semiconductor devices. The interest is motivated by improved electrostatic control in cylindrical geometry possibility utilize heterostructures transistor design. Currently, nanowire transistors been realized both III-Vs group IV materials employing top-down well bottom-up technologies. In this review, we give overview of field and,...

A novel method that reveals the spatial distribution of border traps in III-V metal-oxide-semiconductor field-effect transistors (MOSFETs) is presented. The increase transconductance with frequency explored a very wide range (1 Hz-70 GHz) and distributed RC network used to model oxide trap capacitances. An evaluation vertical InAs nanowire MOSFETs surface-channel InGaAs Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O...

We demonstrate a vertical InAs nanowire MOSFET integrated on Si substrate with an extrinsic peak cut-off frequency of 103 GHz and maximum oscillation 155 GHz. The transistor has transconductance 730 mS/mm is based arrays nanowires gate-all-around high-κ gate dielectric. Furthermore, small-signal modeling shows ~80% reduction the total parasitic capacitance when metal pad overlap in transistors reduced through additional patterning.

We present a vertical nanowire InAs/GaAsSb/GaSb TFET with highly scaled InAs diameter (20 nm). The device exhibits minimum subthreshold swing of 48 mV/dec. for V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ds</inf> = 0.1–0.5 and achieves an I xmlns:xlink="http://www.w3.org/1999/xlink">on</inf> 10.6 μA/μm xmlns:xlink="http://www.w3.org/1999/xlink">off</inf> 1 nA/μm at 0.3 V. lowest achieved is 44 0.05 Furthermore, benchmarking performed...

Tunnel field-effect transistors with ability to operate well below the thermal limit (with a demonstrated 43 mV/decade at VDS = 0.1 V) are characterized in this paper. Based on 88 devices, impact of low subthreshold swing overall performance is studied. Furthermore, correlation between parameters that important for device characterization determined.

We present temperature dependent electrical measurements on InSb and InAs nanowire field-effect transistors (FETs). The FETs are fabricated from InAs/InSb heterostructure nanowires, where one complete transistor is defined within each of the two segments. Both n-type with good current saturation low voltage operation. off-current for FET shows a strong dependence, which we attribute to barrier lowering due an increased band-to-band tunneling in drain part channel.

The ever-growing demand on high-performance electronics has generated transistors with very impressive figures of merit (Radosavljevic et al., IEEE Int. Devices Meeting 2009, 1–4 and Cho 2011, 15.1.1–15.1.4). continued scaling the supply voltage field-effect transistors, such as tunnel (TFETs), requires implementation advanced transistor architectures including FinFETs nanowire devices. Moreover, integration novel materials high electron mobilities, III–V semiconductors graphene, are also...

Thin high-κ oxide films on InAs, formed by atomic layer deposition, are the key to achieve high-speed metal-oxide-semiconductor devices. We have studied native and interface between InAs 2 nm thick Al2O3 or HfO2 layers using synchrotron x-ray photoemission spectroscopy. Both lead a strong reduction, obtaining less than 10% of As-oxides 50% In-oxides, depending deposition temperature. The ratio In- is determined be 2:1. exact composition influence different oxidation states suboxides...

In this letter, we present a 15-nm-diameter InAs nanowire MOSFET with excellent on and off characteristics. An n-i-n doping profile was used to reduce the source drain resistances, an Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> /HfO bilayer introduced in high- process. The nanowires exhibit high drive currents, up 1.25 A/mm, normalized circumference, current densities 34 MA/cm...

We have developed a self-aligned L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g</sub> = 55 nm In xmlns:xlink="http://www.w3.org/1999/xlink">0.53</sub> Ga xmlns:xlink="http://www.w3.org/1999/xlink">0.47</sub> As MOSFET incorporating metal-organic chemical vapor deposition regrown n <sup xmlns:xlink="http://www.w3.org/1999/xlink">++</sup> source and drain regions, which enables record low on-resistance of 199 Ωμm. The regrowth process...

In this paper, InAs/GaSb nanowire tunnel field-effect transistors (TFETs) are studied theoretically and experimentally. A 2-band 1-D analytic tunneling model is used to calculate the on- off-current levels of TFETs with staggered source/channel band alignment. Experimental results from lateral shown, as well first on integration vertical Si substrates.

This paper presents dc and RF characterization as well modeling of vertical InAs nanowire (NW) MOSFETs with L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> =200 nm Al xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> /HfO high-κ dielectric. Measurements at V xmlns:xlink="http://www.w3.org/1999/xlink">DS</sub> =0.5 show that high transconductance (g...

We demonstrate improved performance due to enhanced electrostatic control achieved by diameter scaling and gate placement in vertical InAs-GaSb tunneling field-effect transistors integrated on Si substrates. The best subthreshold swing, 68 mV/decade at V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS</sub> = 0.3 V, was for a device with 20-nm InAs diameter. ON-current the same 35 μA/μm xmlns:xlink="http://www.w3.org/1999/xlink">GS</sub> 0.5...

We have investigated the scaling properties of [111] InAs nanowire MOSFETs in ballistic limit. The band structure has been calculated with an sp <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> d xmlns:xlink="http://www.w3.org/1999/xlink">5</sup> s* tight-binding model for diameters between 2 and 25 nm. Both effective gap masses increase confinement. Using atomistic dispersion relations, currents corresponding capacitances a...

In this paper we present a 55 nm gate length <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.53</sub> Ga xmlns:xlink="http://www.w3.org/1999/xlink">0.47</sub> As MOSFET with extrinsic transconductance of 1.9 mS/μm and on-resistance 199 Ωμm. The self-aligned is formed using metalorganic chemical vapor deposition regrowth highly doped source drain access regions. fabricated 140 devices shows low subthreshold swing 79 mV/decade, which attributed...

We demonstrate InGaAs multigate MOSFETs, so-called FinFETs. The lateral nanowires constituting the channel in these devices have been formed using selective area regrowth, where surfaces of are crystallographic planes. Lg = 32 nm exhibit peak transconductance 1.8 mS/μm at V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ds</sub> 0.5 V. also report on RF characterization devices. A small-signal hybrid-π model is developed, which includes both...

We present experimental data from vertical InAs/InGaAsSb/GaSb nanowire tunnel field-effect transistors with channel diameter scaled down to 10 nm and ability reach a point subthreshold swing of 35 mV/decade at V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS</sub> = 0.05 V. Furthermore, the impact drain, channel, source scaling on currents are studied. Impact gate-overlap is more evident for devices highly due strong reduction current. small...

We report extremely low specific contact resistivity (ρc) nonalloyed Ohmic contacts to n-type In0.53Ga0.47As, lattice matched InP. Contacts were formed by oxidizing the semiconductor surface through exposure ultraviolet-generated ozone, subsequently immersing wafer in ammonium hydroxide (NH4OH, 14.8 normality), and finally depositing either Ti∕Pd∕Au metal electron-beam evaporation or TiW vacuum sputtering. exhibited ρc of (0.73±0.44)Ωμm2—i.e., (7.3±4.4)×10−9Ωcm2—while (0.84±0.48)Ωμm2. The...

The influence of InAs orientations and high-k oxide deposition conditions on the electrical structural quality Au/W/Al2O3/InAs metal-oxide-semiconductor capacitors was investigated using capacitance-voltage (C-V) x-ray photoemission spectroscopy techniques. results suggest that interface traps around conduction band edge are correlated to As-oxide amount, while less those As-As bonds In-oxides. deposited Al determines border trap density, hence capacitance frequency dispersion. comparison...

III–V nanowire (NW) transistors are an emerging technology with the prospect of high performance and low power dissipation. Performance evaluations these devices, however, have focused mostly on intrinsic properties NW, excluding any parasitic elements. In this paper, a NW transistor architecture is investigated, based array realistic footprint. Based scaling rules for structural parameters, 3-D representations generated, capacitances calculated. A complete optimization structure performed...