A5025540737- 3D IC and TSV technologies
- Advancements in Semiconductor Devices and Circuit Design
- Radio Frequency Integrated Circuit Design
- Semiconductor materials and devices
- Analog and Mixed-Signal Circuit Design
- Additive Manufacturing and 3D Printing Technologies
- Silicon Carbide Semiconductor Technologies
- Electronic Packaging and Soldering Technologies
- Nanofabrication and Lithography Techniques
- Advanced Surface Polishing Techniques
- Electromagnetic Compatibility and Noise Suppression
- Acoustic Wave Resonator Technologies
- Microwave Engineering and Waveguides
- Copper Interconnects and Reliability
- Advanced Power Amplifier Design
- Quantum and electron transport phenomena
- VLSI and Analog Circuit Testing
- Electrostatic Discharge in Electronics
Centre National de la Recherche Scientifique
2011-2023
STMicroelectronics (France)
2010-2023
Institut polytechnique de Grenoble
2021-2023
Université Grenoble Alpes
2021-2023
STMicroelectronics (Czechia)
2021
STMicroelectronics (Switzerland)
2009-2010
This paper presents a 7-parameter analytical model of the MOS transistor based on inversion charge targeted at development simplified circuit design methodologies that take into account physics transistor. The proposed design-oriented allows for first time to describe both main short-channel effects advanced nanometric technologies and dependence drain current voltage, while remains valid all bias regimes (from weak strong inversion) operating regions (linear saturated). A simple procedure...
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In this paper, we present some process developments and polymer material evaluations done to achieve the complete filling of 3D-WLP via. The test wafers used for these studies were either blankets with several via sizes specifically designed determine window, or patterns stacking which result from a real set-top box demonstrator. Initially, integration scheme demonstrator required is presented. Then different structures needed characterize behavior are described. Two methods exposed...
This paper deals with an innovative via-last TSV polymer filling process dedicated to straight (non-slopped), high aspect ratio (2:1 5:1) TSV, partially filled copper. New polymers were investigated for this purpose. Firstly, the need a is pointed out. Potential reliability issues added by new are developed through finite element modelling. Secondly, and optimization phase in order obtain void free inside presented. A complete integration of on electrical test vehicle then performed....
This paper deals with the development of a process for medium density through silicon via (TSV) polymer filling. solution is driven by reliability considerations. Firstly, set specifications concerning selection presented. Secondly, optimization two kinds polymers presented: liquid resin and dry film resist. Issues both solutions are also discussed. Different types TSV studied (shapes dimensions). Finally, material characterizations achieved in order to determine ability be integrated 3D...
This paper presents a simple and efficient methodology for LNA design which uses the inversion level of transistor as parameter in order to optimize energy efficiency. The method but accurate 7 parameter-based model valid all regions operation allows an preliminary sizing based on analytical study. proposed describes main short-channel effects advanced technologies evaluation nonlinearity. A use case using 28 nm FD-SOI technology is reflect that well suited designs at weak moderate...
A minimalist MOSFET model for circuit simulation with only five DC parameters written in Verilog-A is presented. The can be extracted from direct and simple methods common simulators. characteristics of transistors both 180-nm bulk CMOS 28-nm FD-SOI technologies generated by the five-parameter are compared those BSIM UTSOI2 models, respectively. some basic circuits using proposed 5-DC-parameter shows good matching model, at benefit a much simpler set parameters.
In this paper, polymer filling of medium density (40 μm diameter and 120 depth) via-last Through Silicon Via (TSV) is investigated. Firstly, a set specifications for the selection established discussed. Secondly, an adequate process its optimization are developed. The overburden thickness planarization issues also taken into account, since should passivate copper redistribution layer on backside surface wafer. Material characterizations then performed in order to obtain relevant properties...
This paper presents the design of a tunable multimode inductorless Low Noise Amplifier (LNA) based on an active $g_{m} -$boosting Common Gate (CG) architecture. The tunability is achieved through discrete coarse mode selection followed by continuous fine-tuning thanks to back gate Fully-Depleted Silicon-On-Insulator (FD-SOI) technology. It demonstrates capability offered body bias implement finely architectures. proposed LNA targets Long-Term Evolution for machines (LTE-M) and Narrowband IoT...
This paper presents a simple and efficient methodology for Resistive Feedback LNAs (RF-LNAs) design which uses the inversion level of transistor as parameter in order to optimize energy efficiency. The method 4 parameter-based model valid all regions operation allows preliminary sizing based on an analytical study. A practical 28 nm FD-SOI technology shows that this is well suited at low moderate advanced simulation-based studies are often used by designer early stage. designed LNA consumes...
This paper presents a design-oriented MOS transistor model that uses only 7 parameters for analytically describing the MOSFET behavior. Based on inversion charge, it accounts most relevant short-channel effects in advanced technologies. The provides analytical relations transconductances, output conductance, and nonlinearities of simple circuit design. is validated using 28nm FD-SOI technology from STMicroelectronics compared to state-of-the-art 4-parameter demonstrate advantages proposed...
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This work presents a survey based on more than 200 published papers related to sub-6 GHz wideband LNAs [1]. It investigates the trends with respect technology node. Moreover, it proposes comparison between most used topologies regarding their main performance metrics such as gain, bandwidth, noise figure, power consumption and linearity. Based this study, analytical predictions can be verified appropriate architectures targeting given set of specifications easily selected. The analysis...