An ultra-low-power common-gate low noise amplifier (CG-LNA) for 2.4 GHz wireless sensor network (WSN) applications is proposed in this letter. The current-reuse and active <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$g_{\rm m}$</tex></formula> -boosting techniques are utilized. analysis, design method measurement results shown. implemented prototype using 0.18 Notation="TeX">$\mu$</tex></formula>...

This paper describes a ultra-wideband (UWB) three-stage cascaded high gain amplifier with low group delay variation for phased-array radar system. The shunt inductor at the input not only provides an electrostatic discharge (ESD) path to ground, but also introduces new notch S11, thus extending matching bandwidth. Staggered tuning of load impedance peaks each stage facilitates balance between flat and variation. output further enhances overall while reinforcing bandwidth stability through...

This brief presents a CMOS wideband passive balun low noise amplifier (LNA) based on magnetically coupled resonator (MCR) matching network. The theoretical analysis, expression derivation and simulation verification of the impedance rise with frequency MCR network is presented for first time. proposed LNA was fabricated in 22-nm technology, which achieves maximum power gain 15.7 dB, figure (NF) 1.46–1.96 dB. 3-dB bandwidth ranges from 2.1–5.2 GHz. minimum input at 1dB compression point...

A new high performance charge pump circuit is designed and realized in 0.18 μm CMOS process. wide input ranged rail-to-rail operational amplifier self-biasing cascode current mirror are used to enable the be well matched a output voltage range. Furthermore, method of adding precharging source proposed increase initial current, which will speed up settling time CPPLLs. Test results show that mismatching can less than 0.4% range 0.4 1.7 V, with 100 μA 70 μA. The average power consumption...

A fully integrated 6–18 GHz bulk CMOS ultra-wideband (UWB) gain-compensation amplifier for phased-array radar system based on SMIC 40-nm process is presented in this paper. Combined with dual-branch input matching network, three-stage cascaded amplification and both the inductive series- shunt-peaking techniques, gain 3-dB bandwidth (BW) further extended. The fabricated UWB achieves a flat of 8.7–13.3 dB an averaged noise figure (NF) 5.75 return loss better than −15.1 dB. Measured 1-dB...

A fully integrated 6-15.3 GHz active digital step attenuator (DSA) with 5-bit gain control for phased-array radar system in SMIC 40-nm CMOS technology is presented this brief. Based on a novel current-tuning variable amplifier (VGA)-topology, amplitude over wider band achieved. The main amplification common-source (CS) transistor was designed to operate the linear region larger attenuation range. fabricated DSA exhibits 15.5-dB tuning range 0.5-dB step, constant input and output impedance...

A low voltage multi-band all PMOS VCO was fabricated in a 0.18-/spl mu/m CMOS process. By using combination of inductor and capacitor switching, four band (2.4, 2.5, 4.7 5 GHz) operation realized single VCO. The with 1-V power supply has phase noises at 1-MHz offset -126 dBc/Hz GHz -134 2.4 GHz, respectively. It the lowest noise among VCOs presented to date bands. consumes 4.6 mW for 2.5 6 operations,

In order to improve the temperature stability of DC-contact RF MEMS switch, a thermal buckle-beam structure is implemented. The switch pull-in voltage versus not only improved, but also impact stress and gradient on drive suppressed. Test results show that less sensitive between -20 °C 100 °C. variable rate about -120 mV/°C. performance stable, isolation almost independent temperature. After being annealed at 280 for 12 hours, our samples, which are suitable packaging, have than 1.5% change...

A 3-bit microelectromechanical system (MEMS) digital attenuator is designed with 0–20 GHz bandwidth. The attenuation ranges from 0 to 35 dB 5 step. attenuator, the coplanar waveguide (CPW), implemented by surface sacrificial layer technology. DC-contact MEMS switches three contact dimples are symmetrically placed around T type resistor network, making minimum in number and structure compact. Through lumped parameter method, has good terminal matches different states. test results show that...

This paper presents two new strain gauge bridge-to-pulse position modulation (PPM) converters. They have been developed in 2-/spl mu/m BiCMOS technology. The first one uses a chopper amplifier and voltage-to-time converter associated feedback loop. topology mainly exhibits an automatic offset cancellation capability, ratiometric transfer function, 10-b accuracy. second is voltage-to-frequency using the switched-capacitor (SC) technique. It optimized version terms of size minimization noise...

This brief presents a nano-ampere CMOS current reference (CCR) for low power application with wide temperature range from -40°C to 120°C. The is generated by the division of temperature-independent voltage and resistance in simple way. based on threshold difference between two same-type NMOS transistors different channel lengths working subthreshold region, while made up poly resistors, whose coefficients are opposite. By designing allow small resistance, CCR circuit takes chip area...

A 5 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sup> -order Chebyshev active RC complex filter for wireless sensor networks with automatic frequency tuning is presented in this paper. This synthesized from low-pass LC prototype, and designed using leapfrog structure. An used to prevent the deviation of constant filter. fabricated TSMC 0.18μm CMOS process. The measurement results show that passband gain about 16dB ripple 1.5dB. It...

A broadband low-noise amplifier (LNA) is proposed. The active gm-boosting technique utilised to reduce the common-gate (CG) LNA noise figure and improve gain. An implemented prototype using 0.13 μm CMOS technology evaluated on-wafer probing. S11 S22 are below − 10 dB across 0.1–5 GHz. Measurements show a power gain of 18.3 with 3 bandwidth from 100 MHz 2.1 GHz an IIP3 7 dBm at 2 measured better than 2.5 GHz, 4.5 5 500 it obtains its minimum value 1.8 dB. consumes 14 mW 1.5 V supply occupies...

The balance compensating techniques for asymmetric Marchand balun are presented in this letter. amplitude and phase difference characterized explicitly by S <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">21</sub> xmlns:xlink="http://www.w3.org/1999/xlink">31</sub> , from which the factors responsible determined. Finally, two baluns, have normal enhanced compensation, respectively, designed fabricated a 0.18 μm CMOS technology demonstration....

A novel Charge Pump (CP) circuit with high performance is introduced in this paper. rail-to-rail operational amplifier used to enable the CP charge and discharge currents be match well a wide output voltage range. unity-gain adopted eliminate current sharing problem. Besides, initial shortens settling time of pump phase-locked-loops (CPPLLs). The proposed designed realized 0.18µm CMOS process. test results show that mismatch rate can less than 0.5% range 0.23V 1.72V, 100µA precharging 109µA....

This paper presents a low-power low-IF RF frontend for 2.4GHz wireless sensor networks (WSN) in 0.18μm CMOS technology. The consists of variable gain low noise amplifier (VG-LNA), quadrature passive mixer and divide-by-two circuit which generates the differential LO signals balanced mixer. effect input parasitic capacitance on inductively degenerated common source LNA's impedance is analyzed detail. An external LC network was used to achieve matching under power consumption. proposed VG-LNA...

This paper presents a 6-18 GHz active 6-bit phase shifter based on vector-sum technique in 0.13-μm SiGe BiCMOS technology for X- and Ku-band phased arrays. An input Marchand balun an L-C resonance-based quadrature all-pass filter are used to generate two orthogonal vectors with high I/Q accuracy linearity over wide frequency band. The reference signals then fed into VGAs, of which the gains adjusted integrated current-mode DAC achieve resolution between 0-360°. shows 3.12 dB power gain at...

A Gm−C complex filter with on-chip automatic tuning for wireless sensor networks is designed and implemented using 0.18 μm CMOS process. This synthesized from a low-pass 5th-order Chebyshev RLC ladder prototype by means of capacitors fully balanced transconductors. conventional phase-locked loop used to realize the both center frequency bandwidth control. The centered at 2 MHz 2.4 MHz. measured results show that provides more than 45 dB image rejection while ripple in pass-band less 1.2 dB....

A wideband 2–3 GHz three-stage low noise amplifier (LNA) featuring current reuse, cascaded L-type input matching network (IMN), and optimized multiple gated transistors method (MGTR) using 0.18-μm CMOS technology is presented in this paper. The current-reused topology employed the first two stages to reduce power consumption. For a matching, common gate (CG) adopted. Moreover, IMN composed of single networks series proposed for time. To improve linearity performance, MGTR taking both...

A low voltage power receiver supporting 780/868/915/2400 MHz ZigBee bands is presented in this paper. The exploiting low-IF architecture consists of a RF-to-BB (baseband) current reuse front-end, Gm-C based variable gain complex band-pass filter (CBPF) for image rejection and four stages limiting amplifiers which saturate IF signal demodulation. proposed chip implemented TSMC 180 nm CMOS technology with metal-insulator-metal (MIM) capacitors. PCB measurement results show that the has 45.9 dB...

This article describes a wideband low-noise frequency synthesizer implemented in 0.13-μm SiGe BiCMOS process for 5G millimeter-wave applications. To extend the range while reducing phase noise, fundamental voltage-controlled oscillator (VCO) array including four Colpitts VCO cores with switchable bias circuits is adopted proposed synthesizer. A ring-oscillator-based injection locked divider utilized as divideby-2 prescaler, and its bandwidth optimized based on new injection-locked behavior...

This paper proposed an X-band 6-bit passive phase shifter (PS) designed in 0.18 μ m silicon-on-insulator (SOI) CMOS technology, which solves the key problem of high integration degree, low power, and a small size T/R module. The switched-topology is employed to achieve broadband flat shift. ESD circuit driver are also integrated PS. It covers frequency band from 7.5 10.5 GHz with EMS error less than 7.5°. input output VSWRs 2 insertion loss (IL) between 8-14 dB across GHz, maximum IL...

This work presents a 24 ​GHz integrated Phase-Locked Loop in 60 sliding-IF transceiver for IEEE 802.15.3c standard with low phase noise. For noise, varactor and MOM cap combination method is applied this PLL. The capacitor bank optimized to decrease the noise folding from circuit within method. analog PLL fabricated 65 ​nm CMOS technology of −98.8 dBc/[email protected] ​MHz, reference spur −62.4 dBc. power consumption 45.6 ​mW, including output buffer.