In this paper, we propose four 4:2 compressors, which have the flexibility of switching between exact and approximate operating modes. mode, these dual-quality compressors provide higher speeds lower power consumptions at cost accuracy. Each has its own level accuracy in mode as well different delays dissipations Using structures parallel multipliers provides configurable whose accuracies (as their powers speeds) may change dynamically during runtime. The efficiencies a 32-bit Dadda...

In this brief, we propose a fast yet energy-efficient reconfigurable approximate carry look-ahead adder (RAP-CLA). This has the ability of switching between and exact operating modes making it suitable for both error-resilient applications. The structure, which is more area power efficient than state-of-the-art adders, achieved by some modifications to conventional look ahead (CLA). efficacy proposed RAP-CLA evaluated comparing its characteristics those two adders as well (exact) CLA in 15...

A scalable approximate multiplier, called truncation- and rounding-based multiplier (TOSAM) is presented, which reduces the number of partial products by truncating each input operands based on their leading one-bit position. In proposed design, multiplication performed shift, add, small fixed-width operations resulting in large improvements energy consumption area occupation compared to those exact multiplier. To improve total accuracy, part are rounded nearest odd number. Because truncated...

Issues related to substrate noise in system-on-chip design are described including the physical phenomena responsible for its creation, coupling transmission mechanisms and media, parameters affecting strength, impact on mixed-signal integrated circuits. Design guidelines best practices minimize generation, transmission, reception of outlined, different modeling approaches computer simulation methods used quantifying presented. Finally, experiments that validate mitigation techniques reviewed

In this paper, a reverse carry propagate adder (RCPA) is presented. the RCPA structure, signal propagates in counter-flow manner from most significant bit to least bit; hence, input has higher significance than output carry. This method of propagation leads stability presence delay variations. Three implementations full-adder (RCPFA) cell with different delay, power, energy, and accuracy levels are introduced. The proposed structure may be combined an exact (forward) form hybrid adders...

In this brief, a low energy consumption block-based carry speculative approximate adder is proposed. Its structure based on partitioning the into some non-overlapped summation blocks whose structures may be selected from both propagate and parallel-prefix adders. Here, output of each block speculated input operands itself those next block. adder, length chain reduced to two (worst case), where in most cases only one employed calculate leading lower average delay. addition, increase accuracy...

In this article, a technique, based on using Residue Number System (RNS) is suggested to improve the energy efficiency of Deep Neural Networks (DNNs). DNN architecture, which fully RNS-based, only weights and primary inputs in main memory are binary number system (BNS). The called Res-DNN, offers high saving while requiring higher bit count for data handle overflow compared that BNS one. Scaling techniques processing elements employed RNS-based computations make computation widths same as...

In this paper, two static random access memory (SRAM) cells that reduce the power dissipation due to gate and subthreshold leakage currents are presented. The first cell structure results in reduced voltages for NMOS pass transistors, thus lowers current. It reduces current by increasing ground level during idle (inactive) mode. second makes use of PMOS transistors lower addition, dual threshold voltage technology with forward body biasing is utilized while maintaining performance. Compared...

In this paper, we present a carry skip adder (CSKA) structure that has higher speed yet lower energy consumption compared with the conventional one. The enhancement is achieved by applying concatenation and incrementation schemes to improve efficiency of CSKA (Conv-CSKA) structure. addition, instead utilizing multiplexer logic, proposed makes use AND-OR-Invert (AOI) OR-AND-Invert (OAI) compound gates for logic. may be realized both fixed stage size variable styles, wherein latter further...

In this paper, we present a high speed yet energy efficient approximate divider where the division operation is performed by multiplying dividend inverse of divisor. structure, truncated value multiplied exactly (approximately) To assess efficacy proposed divider, its design parameters are extracted and compared to those number prior art dividers in 45nm CMOS technology. Results reveal that structure provides 66% 52% improvements area consumption, respectively, most advanced divider....

In this paper, a high speed yet energy-efficient approximate divider for error resilient applications is proposed. For the division operation, divisor rounded to value with specific form resulting in transformation of operation multiplication one. The proposed enjoys flexibility increasing accuracy at price higher delay and hardware usage. efficacy evaluated comparison three different implementations SRT divider. results show that energy consumption are, on average, 14 300 times smaller than...

In this paper, we propose an ultra low-power analog neuromorphic circuit to be trained process sensory data in the Internet of Things smart sensors where and are efficient computing is required. To reduce operating voltage while maintaining performance, focus on designing a memristive without employing operational amplifiers. Therefore, use CMOS inverters as neurons our circuit. We also mixed-signal input/output interfaces make connectable other digital components such embedded processor....

In this article, we present an energy-efficient approximate CGRA (X-CGRA). Instead of conventional exact arithmetic units, it employs configurable adders and multipliers in the so-called quality-scalable processing elements (QSPEs). Furthermore, structure functionality other architectural components, like context memory, are modified based on operating modes QSPEs. The quality reconfigurability X-CGRA makes amenable for both error-resilient nonresilient applications. To map applications...

In this brief, a low resource utilization field-programmable gate array (FPGA)-based long short-term memory (LSTM) network architecture for accelerating the inference phase is presented. The has low-power and high-speed features that are achieved through overlapping timing of operations pipelining datapath. Moreover, requires negligible internal size storing intermediate data leading to simple routing, which provides lower interconnect delay (higher operating frequency). A designer may...

The paper presents new low-power flip-flops which are faster compared to previously proposed structures. single-edge-triggered flip-flop, called the MHLFF (modified hybrid latch flip-flop), reduces power dissipation of HLFF (hybrid flip-flop) by avoiding unnecessary node transitions. To reduce consumption flip-flop further, double-edge-triggered modified (DMHLFF) is also proposed. in clock tree reduced halving frequency for same throughput. In addition low power, speed higher while area not...

As technology shrinks, the power dissipated by links of a network-on-chip (NoC) starts to compete with other elements communication subsystem, namely, routers and network interfaces (NIs). In this paper, we present set data encoding schemes aimed at reducing an NoC. The proposed are general transparent respect underlying NoC fabric (i.e., their application does not require any modification link architecture). Experiments carried out on both synthetic real traffic scenarios show effectiveness...

In this paper, we present a framework for analytically estimating the output quality of common digital signal processing (DSP) blocks that utilize approximate adders. The is based on considering error adders as an additive noise (approximation noise) disturbs DSP block in question. A theoretical modeling approach describing power approximation which integral spectral density over bandwidth, developed. qualities blocks, such finite impulse response filter, discrete cosine transform, and fast...

Thermal stress including temperature gradients in time and space, as well thermal cycling, influences lifetime reliability performance of modern multiprocessor systems-on-chip (MPSoCs). Conventional power management techniques considering the peak temperature/power consumption do not provide a comprehensive solution to avoid high spatial temporal variations. This work presents TheSPoT, novel multilevel stress-aware approach for MPSoCs. At top level, core consolidation deconsolidation is...

Coarse-Grained Reconfigurable Architectures (CGRAs) provide tradeoff between the energy-efficiency of Application Specific Integrated Circuits (ASICs) and flexibility General Purpose Processors (GPPs). State-of-the-art CGRAs only support exact architectures precise application executions. However, a majority streaming applications such as multimedia digital signal processing, which are amenable to CGRAs, inherently error resilient. Therefore, these can greatly benefit from emerging trend...

In this paper we propose a pseudo adaptive routing which is an extension of classic XY routing. We consider mesh topology for evaluating proposed Our switches use algorithm. The load in the center network ordinary much higher rather than total average. This extra on can cause spot hot. main objective our algorithm to distribute load. One advantages distributing balanced temperature mesh. has two deterministic and modes that status neighbors each switch used decide mode must be selected....

In this paper, a low-power structure called bypass zero, feed A directly (BZ-FAD) for shift-and-add multipliers is proposed. The architecture considerably lowers the switching activity of conventional multipliers. modifications to multiplier which multiplies <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">A</i> by xmlns:xlink="http://www.w3.org/1999/xlink">B</i> include removal shifting register, direct feeding adder, bypassing adder whenever...