A5053490898- Advancements in Semiconductor Devices and Circuit Design
- Semiconductor materials and devices
- Parallel Computing and Optimization Techniques
- Electrostatic Discharge in Electronics
- Silicon Carbide Semiconductor Technologies
- Ferroelectric and Negative Capacitance Devices
- Low-power high-performance VLSI design
- Advanced Data Storage Technologies
- Physical Unclonable Functions (PUFs) and Hardware Security
- Integrated Circuits and Semiconductor Failure Analysis
- Distributed and Parallel Computing Systems
- Interconnection Networks and Systems
- Security and Verification in Computing
- Cryptographic Implementations and Security
- 3D IC and TSV technologies
University of Illinois Urbana-Champaign
2023-2025
Fairchild Semiconductor (United States)
2003
The ever-growing demands for memory with larger capacity and higher bandwidth have driven recent innovations on expansion disaggregation technologies based Compute eXpress Link (CXL). Especially, CXL-based technology has recently gained notable attention its ability not only to economically expand but also decouple from a specific interface of the CPU. However, since CXL devices been widely available, they emulated using DDR in remote NUMA node. In this paper, first time, we comprehensively...
The demand for accurate information about the internal structure and characteristics of DRAM has been on rise. Recent studies have explored to improve processing in memory, enhance reliability, mitigate a vulnerability known as rowhammer. However, manufacturers only disclose limited through official documents, making it difficult find specific actual devices. This paper presents reliable findings using activate-induced bitflips (AIBs), retention time test, row-copy operation. While previous...
RESURF LDMOS transistors are utilized in high side driver applications and other that mandate electrical isolation between source substrate by using isolated technology. However, the BCD process conventional structures cannot provide efficiency vertical NPN due to dependence of BV/sub dss/ (source drain breakdown voltage) upon epi thickness. In this paper, we propose a new LDMOS. With use n-well near region, can avoid electric field concentration below region. P-well dose, p-well length...
In this paper, for the first time, we suggest a novel high voltage, speed and latch-up free NPN transistor PNP fabrication technology using PBSOI (Patterned Bonded Silicon On Insulator) STI (Shallow Trench Isolation) technology. Using technique, can easily control breakdown voltage (BVceo) without problem of P+B/L out-diffusion. process, after diffusion well (collector), Buried Layer is diffused on well. addition, unlike prior that devices are fabricated in epitaxial layer, proposed formed...
The demand for precise information on DRAM microarchitectures and error characteristics has surged, driven by the need to explore processing in memory, enhance reliability, mitigate security vulnerability. Nonetheless, manufacturers have disclosed only a limited amount of information, making it difficult find specific their microarchitectures. This paper addresses this gap presenting more rigorous findings commodity chips impacts activate-induced bitflips (AIBs), such as RowHammer RowPress....
This paper presents the structure and method of effective ESD protection reliability in high voltage LDMOS with Sense Source (SenseFET) which is newly proposed 1-chip process for smart power ICs. have been investigated experimentally theoretically by employing two-dimensional device simulators. The cause failure turned out to be failed on experiment more than itself. distance between drain pad must long enough closely located a lot Ground contact if possible.
The demand for accurate information about the internal structure and characteristics of dynamic random-access memory (DRAM) has been on rise. Recent studies have explored DRAM to improve processing in memory, enhance reliability, mitigate a vulnerability known as rowhammer. However, manufacturers only disclose limited through official documents, making it difficult find specific actual devices. This paper presents reliable findings using activate-induced bitflips (AIBs), retention time test,...
In order to solve the ESD problem, we propose a circuit which includes protection diode with collector-base shorted emitter of npn transistor. Simulation results show that it is possible add an CB in form parallel for relieving impact without generating melting point metal.