Kostas Siozios

ORCID: 0000-0002-0285-2202
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About
Contact & Profiles
Research Areas
  • Embedded Systems Design Techniques
  • Interconnection Networks and Systems
  • VLSI and FPGA Design Techniques
  • Parallel Computing and Optimization Techniques
  • 3D IC and TSV technologies
  • Low-power high-performance VLSI design
  • VLSI and Analog Circuit Testing
  • Smart Grid Energy Management
  • Advanced Memory and Neural Computing
  • Building Energy and Comfort Optimization
  • Smart Grid Security and Resilience
  • Advancements in Semiconductor Devices and Circuit Design
  • Radiation Effects in Electronics
  • Robotics and Sensor-Based Localization
  • Advanced Image and Video Retrieval Techniques
  • Semiconductor materials and devices
  • Analog and Mixed-Signal Circuit Design
  • Energy Harvesting in Wireless Networks
  • Cloud Computing and Resource Management
  • Neural Networks and Applications
  • IoT and Edge/Fog Computing
  • CCD and CMOS Imaging Sensors
  • Innovative Energy Harvesting Technologies
  • Indoor and Outdoor Localization Technologies
  • Manufacturing Process and Optimization

Aristotle University of Thessaloniki
2016-2025

Karlsruhe Institute of Technology
2024

University of Patras
2022-2024

Michigan United
2024

University of Michigan
2024

Brno University of Technology
2024

Israel Electric (Israel)
2023

Politecnico di Milano
2022

University of Bremen
2022

University of California, Santa Barbara
2022

Current state-of-the-art employs approximate multipliers to address the highly increased power demands of DNN accelerators. However, evaluating accuracy DNNs is cumbersome due lack adequate support for arithmetic in frameworks. We this inefficiency by presenting AdaPT, a fast emulation framework that extends PyTorch inference as well approximation-aware retraining. AdaPT can be seamlessly deployed and compatible with most DNNs. evaluate on several models application fields including CNNs,...

10.1109/tcad.2022.3212645 article EN IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 2022-10-06

Deep Neural Networks (DNNs) have shown significant advantages in a wide variety of domains. However, DNNs are becoming computationally intensive and energy hungry at an exponential pace, while the same time, there is vast demand for running sophisticated DNN-based services on resource constrained embedded devices. In this paper, we target energy-efficient inference DNN accelerators. To that end, propose automated framework to compress hardware-aware manner by jointly employing pruning...

10.1109/tetc.2023.3346944 article EN IEEE Transactions on Emerging Topics in Computing 2024-01-03

System design, especially for low power embedded applications often profit from a heterogeneous target hardware platform. The application can be partitioned into modules with specific requirements e.g. parallelism or performance in relation to the provided blocks on multicore hardware. result is an optimized mapping and parallel processing lower consumption different cores This paper presents platform consisting of microprocessor field programmable gate array (FPGA) connected via standard...

10.1109/ipdps.2011.135 article EN 2011-05-01

Mars exploration is expected to remain a focus of the scientific community in years come. A rover should be highly autonomous because communication between and terrestrial operation center difficult, vehicle spend as much its traverse time possible moving. Autonomous behavior implies that vision system provides both wide view enable navigation three‐dimensional (3D) reconstruction, at same close‐up ensuring safety providing reliable odometry data. The European Space Agency funded project...

10.1002/rob.21484 article EN Journal of Field Robotics 2013-10-10

Tiny machine learning (TinyML) demands the development of edge solutions that are both low-latency and power-efficient. To achieve these on System-on-Chip (SoC) FPGAs, co-design methodologies, such as hls4ml, have emerged aiming to speed up design process. In this context, fast estimation FPGA’s utilized resources is needed rapidly assess feasibility a design. paper, we propose resource estimator for fully customized (bespoke) multilayer perceptrons (MLPs) designed through hls4ml workflow....

10.3390/electronics14020247 article EN Electronics 2025-01-09

In current reconfigurable architectures, the interconnection structures increasingly contribute more to delay and power consumption. The demand for increased clock frequencies logic density (smaller area footprint) makes problem even important. Three-dimensional (3D) architectures are able alleviate this by accommodating a number of functional layers, each which might be fabricated in different technology. However, benefits such integration technology have not been sufficiently explored yet....

10.1155/2008/764942 article EN cc-by International Journal of Reconfigurable Computing 2008-01-01

Leveraging the inherent error resilience of a large number application domains, approximate computing is established as an efficient design alternative to improve their energy profile. In this brief, we optimal cross-layer arithmetic circuits by enabling voltage overscaling (VOS). Departing from conventional approaches followed today, introduce voltage-driven functional approximation and present VoltAge-Driven nEtlist pRuning (VADER) framework. VADER automated synthesis framework that can be...

10.1109/tvlsi.2019.2900160 article EN IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2019-03-07

Accurate detection of cardiac pathological events is an important part electrocardiogram (ECG) evaluation and subsequent correct treatment the patient. For this purpose, several adaptive filter structures were proposed during past decades for noise cancellation arrhythmia detection. Currently there are a lot devices on market that analyze ECGs, such as patient monitors, stress test systems, Holter analysis able to detect beats classify arrhythmia. This paper proposes system ECG heartbeat...

10.1109/mocast.2019.8742072 article EN 2019-05-01

A heterogeneous interconnect architecture can be a useful approach for the design of 3-D FPGAs. methodology to investigate interconnection schemes FPGAs under different fabrication technologies is proposed. Application proposed on benchmark circuits demonstrates an improvement in delay, power consumption, and total wire-length approximately 41%, 32%, 36%, respectively, as compared 2-D These improvements are additional reducing number interlayer connections. The fewer connections traded off...

10.1145/2133352.2133356 article EN ACM Transactions on Reconfigurable Technology and Systems 2012-03-01

Water scarcity and desertification are considered to be among the greatest challenges of humanity over coming decades. Worldwide, agriculture accounts 69% total water usage, while industry for 23%, urban use 8%. In Greece, a rural development model poor farming practices have resulted in an overwhelming 83% consumption directed uses. Furthermore, excessive combined with existing pesticides fertilizers usage levels creates exponential problems cycle Greece. Taking into account above...

10.1109/patmos.2019.8862146 article EN 2019-07-01

Lately, the advancement in circuit technology combined with design of low cost embedded devices have resulted an infiltration latter into everyday humans' lives. To exploit full potential ubiquitous devices, a network is used for their inter-communication, offering advanced real-time monitoring. This paradigm, known as Internet Things (IoT), steadily consolidated and promises to offer wide variety applications. However, adoption IoT, new challenges arise, such architectures able support...

10.1109/patmos.2017.8106984 article EN 2017-09-01

Recently, a new generation of systems with integrated computational and physical capabilities, also known as CyberPhysical Systems (CPSs), has been introduced. The control these often results in very high-order models imposing great challenges to the analysis design problems. In context this paper, decision-making mechanism for is proposed. Moreover, we introduce virtual prototyping framework implementation customization orchestrators. For evaluation purposes, introduced solution applied...

10.1109/tcst.2019.2922314 article EN IEEE Transactions on Control Systems Technology 2019-07-23

Partial reconfiguration is possible to deliver virtually unlimited hardware resources since it enables dynamic allocation and de-allocation of tasks onto a reconfigurable architecture, while the rest continue operate. However, in order benefit from this flexibility, partial has be appropriately applied. Among others, placement configuration data critical issue affects fragmentation resources. In paper we introduce novel methodology for supporting with usage Just-in-Time (JIT) Compilation...

10.1109/ipdpsw.2012.40 article EN 2012-05-01

Buildings are immensely energy-demanding and this fact is enhanced by the expectation of even more increment energy consumption in future. In order to mitigate problem, a low-cost, flexible high-quality Decision-Making Mechanism for supporting tasks Smart Thermostat proposed. Energy efficiency thermal comfort two primary quantities regarding control performance building's HVAC system. Apart from demonstrating conflicting relationship, they depend not only on dynamics, but also surrounding...

10.1145/3285017.3285024 article EN 2018-10-04

This paper introduces a software supported methodology for exploring/evaluating 3D FPGA architectures. Two new CAD tools are developed: (i) the 3DPRO placement and routing on FPGAs (ii) 3DPower power/energy estimation such We mainly focus our exploration total number of layers amount vertical interconnects (or vias). The efficiency proposed architecture is evaluated by making an exhaustive via connections under Energy×Delay Product criterion. Experimental results demonstrate effectiveness...

10.1109/fpl.2007.4380738 article EN 2007-08-01
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