A5064748988- Advancements in PLL and VCO Technologies
- Advanced Sensor and Control Systems
- Analog and Mixed-Signal Circuit Design
- Optical Network Technologies
- CCD and CMOS Imaging Sensors
- Analytical Chemistry and Sensors
- Advanced Photonic Communication Systems
- Image Processing Techniques and Applications
- Advanced Data Storage Technologies
- Advanced Algorithms and Applications
- Radio Frequency Integrated Circuit Design
- Embedded Systems and FPGA Design
- Real-time simulation and control systems
Hainan University
2024
Chongqing University
2018-2022
In an 8B/10B mode giga-bit-per-second serial data transactions, the de-serialized is sent to a comma detection and word alignment (CDWA) module identify boundaries, which prerequisite in high-speed transceivers such as PCIe, USB JESD204B/C. order ensure that code (/K/-code) can be correctly detected. Ten 10-bit detector cells are adopted typical CDWA module, require complex circuitry enormous power consumption. To overcome these limitations, low-area low-power circuit for JESD204B/C...
This paper presents an area-efficient design of a column-parallel second-order digital decimation filter for ΣΔ analog-to-digital converter-based CMOS image sensor. By using the proposed pre-bitwise-inversion topology having same mathematical function, chip area could be curtailed, where bit-wise-inversion block, required by correlated-double-sampling, is moved to front adder. Following such technique as this, more than six inverters and multiplexers can reduced. also proposes adder scheme...
In this article, a moving accumulative sign filter (MASF) voter model and low-power serial voting circuit are proposed for high-speed clock data recovery (CDR). Different from the previously reported parallel average majority (MV), design is based on MASF algorithm adopts two-stage structure. Only D-flip-flop (DFF) basic logic gates used to realize function of four continuous lead/lag/hold decision signals. The MV realizes signal processing four-phase error information without using...
A novel down-sampling filter named moving accumulative sign (MASF) is proposed for low-power of large-scale binary and ternary data. Besides, the MASF has greatly circuit realization advantages than state-of-the-art cascaded-integrator-comb (CIC) filter, especially in area design. The theory introduced comprehensively, including algorithm model, transfer function, frequency response characteristics. pipeline voting architecture applied to implementation improve speed data processing, which...
Based on the moving average filter, a accumulative sign filter is proposed, its performance analysed comprehensively, and it can be applied to structure of pipeline voter, which used for detection single digital signal, also majority voter two signals. The two-stage has been implemented, only use gates D flip-flop, greatly reduces area power consumption voting circuit. proposed in CDR circuit 40 nm SerDes chip.