Yongsang Yoo

ORCID: 0000-0002-7128-4018
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About
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Research Areas
  • Analog and Mixed-Signal Circuit Design
  • Advanced Sensor and Energy Harvesting Materials
  • Advancements in Semiconductor Devices and Circuit Design
  • CCD and CMOS Imaging Sensors
  • Tactile and Sensory Interactions
  • Generative Adversarial Networks and Image Synthesis
  • Silicon Carbide Semiconductor Technologies
  • Analytical Chemistry and Sensors
  • Low-power high-performance VLSI design
  • Muscle activation and electromyography studies
  • Welding Techniques and Residual Stresses
  • Multimodal Machine Learning Applications
  • Electrostatic Discharge in Electronics
  • Semiconductor Lasers and Optical Devices
  • Advanced MEMS and NEMS Technologies
  • Radio Frequency Integrated Circuit Design
  • Advancements in PLL and VCO Technologies
  • Domain Adaptation and Few-Shot Learning
  • Gas Sensing Nanomaterials and Sensors
  • Digital Media Forensic Detection
  • Semiconductor materials and devices
  • Optical Systems and Laser Technology
  • Advanced Neural Network Applications
  • Advanced Image and Video Retrieval Techniques
  • Advanced Image Processing Techniques

Hanyang University
2021-2023

Yonsei University
2023

Incheon National University
2019-2020

Singapore Institute of Manufacturing Technology
2005

Dongguk University
2003

The recent advance of synthetic image generation and manipulation methods allows us to generate face images close real images. On the other hand, importance identifying increases more protect personal privacy from those. Although some deep learning-based forensic have been developed recently, it is still challenging distinguish generated by such as fake, face2face, swap. To resolve this challenge, we propose a novel generative adversarial ensemble learning method. We train multiple...

10.1109/access.2020.2968612 article EN cc-by IEEE Access 2020-01-01

Crosstalk between the sensor element to be read and other elements in matrix constitutes a critical problem reading passive resistive sensors. Various zero-potential-biasing readout circuits have been proposed solve crosstalk problem, but remains due circuit nonidealities, such as offset finite open-loop gain of amplifiers ON-resistance switches used circuit. Therefore, we propose novel low that can suppress caused by these nonidealities circuits. The main ideas are: 1) including unaddressed...

10.1109/jsen.2023.3234242 article EN IEEE Sensors Journal 2023-01-09

Generating realistic images with fine details are still challenging due to difficulties of training GANs and mode collapse. To resolve this problem, our main idea is that leveraging the knowledge an image classification network, which pre-trained by a large scale dataset (e.g. ImageNet), would improve GAN. By using gradient network (i.e. discriminator) high discriminability during training, we can, therefore, guide generator gradually toward real data region. However, excessive negative...

10.1109/access.2019.2913697 article EN cc-by-nc-nd IEEE Access 2019-01-01

MOSFET mismatch model based on BSIM3v3 for a CMOS 0.13 μm technology using backward propagation of variance (BPV) methodology coupled with Pelgrom basis was developed. Test structures were carefully designed intrinsic drain current characterisation under 4 different gate voltages that vary from weak to strong inversion both linear and saturation regions. Monte Carlo matched pair simulation HSPICE performed verification. The shown be scalable biases sizes physically consistent in predicting...

10.1109/edssc.2007.4450311 article EN IEEE Conference on Electron Devices and Solid-State Circuits 2007-01-01

The choice of technology for today's mixed-signal/RF system-on-chip (SOC) designs has been driven by the performance enhancements and cost advantage derived from scaled CMOS technologies. This paper discusses improvements RF transistors resulting downscaling. Comparisons between SiGe BiCMOS technologies to highlight benefits employing HBT devices in certain applications are made. Other enablements discussed include accurate, scalable models statistical address need design flexibility robust...

10.1109/rfit.2005.1598888 article EN 2005-01-01

In this paper, a 1.8 V 10 bit 300 MSPS CMOS digital-to-analog converter (DAC) is described. The architecture of the D/A based on current steering 8+2 segmented type, which reduces non-linearity errors and other secondary effects. order to achieve high performance converter, novel cell with low spurious deglitching circuit row/column 4 15 inverse thermometer decoder are proposed. To verify performance, device integrated 0.25 /spl mu/m 1-poly 5-metal technology. effective chip area 1.56 mm/sup...

10.1109/apccas.2002.1115245 article EN Asia Pacific Conference on Circuits and Systems 2003-06-26

Continued scaling down of MOSFETs, compounded with limitation in process variation control capabilities, has made MOSFET mismatch more significant for advanced technologies. In order to prevent over compensating design margin, it is important characterize the intrinsic accurately. this paper, test structures are designed study influence back end line (BEOL), multi-fingered layout, and gate protection diode (GPD) on threshold voltage characterization.

10.1109/edssc.2007.4450310 article EN IEEE Conference on Electron Devices and Solid-State Circuits 2007-01-01

As an icon is a means of communication, understanding its concept utmost importance. However, in many cases, icon’s appearance not line with concept. To predict the abstract appearance, we propose compositional learning for icons. The whole predicted by combining components. We Jobicon, ajob symbolizing dataset suitable learning. Jobicon classified components job’s When applied image retrieval model, our demonstrated best performance and

10.1109/bigcomp57234.2023.00047 article EN 2023-02-01

To suppress errors in a touch readout circuit due to display noise, differential sensing using fully amplifiers is widely used. However, conventional methods require additional circuits or increase complexity, thus increasing power consumption and area requiring dummy RX line on the panel. In this study, we propose compact composed of single-ended amplifier while keeping noise suppression so as minimize avoid need for line. The proposed fabricated 0.4 mm2 with 0.35 µm 3.3 V CMOS process...

10.1080/15980316.2022.2154863 article EN cc-by Journal of Information Display 2022-12-12
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