Hae‐Seung Lee

ORCID: 0000-0002-7783-0403
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About
Contact & Profiles
Research Areas
  • Analog and Mixed-Signal Circuit Design
  • Fuel Cells and Related Materials
  • CCD and CMOS Imaging Sensors
  • Membrane-based Ion Separation Techniques
  • Advancements in Semiconductor Devices and Circuit Design
  • Membrane Separation Technologies
  • Advancements in PLL and VCO Technologies
  • Low-power high-performance VLSI design
  • Advanced Battery Materials and Technologies
  • Radio Frequency Integrated Circuit Design
  • Advanced MEMS and NEMS Technologies
  • Membrane Separation and Gas Transport
  • Sensor Technology and Measurement Systems
  • Liver Disease Diagnosis and Treatment
  • Advanced Memory and Neural Computing
  • Integrated Circuits and Semiconductor Failure Analysis
  • Semiconductor Quantum Structures and Devices
  • Physics of Superconductivity and Magnetism
  • Advanced Electrical Measurement Techniques
  • Neuroscience and Neural Engineering
  • 3D IC and TSV technologies
  • Alcohol Consumption and Health Effects
  • Magnetic Field Sensors Techniques
  • Characterization and Applications of Magnetic Nanoparticles
  • Magnetic properties of thin films

Massachusetts Institute of Technology
1997-2024

UCLA Medical Center
2023

Harbor–UCLA Medical Center
2023

Virginia Tech
2007-2017

IIT@MIT
2017

Eulji University
2014

Soonchunhyang University
2010

Cypress Semiconductor Corporation (Japan)
2006

University of California, Berkeley
1983

Abstract Two of the greatest challenges facing 21st century involve providing sustainable supplies clean water and energy, two highly interrelated resources, at affordable costs. Membrane technology is expected to continue dominate purification technologies owing its energy efficiency. However, there a need for improved membranes that have higher flux, are more selective, less prone various types fouling, resistant chemical environment, especially chlorine, these processes. This article...

10.1002/polb.22037 article EN Journal of Polymer Science Part B Polymer Physics 2010-06-25

A high-swing, high-performance CMOS telescopic operational amplifier is described. The high swing of the op-amp achieved by employing tail and current source transistors in deep linear region. resulting degradation differential gain, common-mode rejection ratio (CMRR), other characteristics are compensated applying regulated-cascode gain enhancement a replica-tail feedback technique. prototype has been built 0.81-/spl mu/m process. Operating from power supply 3.3 V, it achieves /spl...

10.1109/4.735542 article EN IEEE Journal of Solid-State Circuits 1998-01-01

A set of power minimization techniques is proposed for pipelined ADC's. These include commutating feedback-capacitors, sharing the op-amp between adjacent stages pipeline, reusing first stage as comparator pre-amp, and exploiting parasitic capacitors common-mode feedback. This low-power design incorporated in an experimental chip fabricated a 1.2-/spl mu/m, double-poly, double-metal CMOS process. At 12-b 5-Msample/s, dissipates 33 mW from 2.5-V analog supply while achieving maximum...

10.1109/4.545805 article EN IEEE Journal of Solid-State Circuits 1996-01-01

Abstract Segmented disulfonated poly(arylene ether sulfone)‐ b ‐polyimide copolymers based on hydrophilic and hydrophobic oligomers were synthesized evaluated for use as proton exchange membranes (PEMs). Amine terminated sulfonated poly (arylene sulfone) anhydride naphthalene polyimide via step growth polymerization including high temperature one‐pot imidization. Synthesis of the multiblock was achieved by an imidization coupling reaction in a m ‐cresol/NMP mixed solvent system, producing...

10.1002/pola.22238 article EN Journal of Polymer Science Part A Polymer Chemistry 2007-09-14

Dynamic performance of high-speed high-resolution digital-to-analog converters (DACs) is limited by distortion at the data switching instants. Inter-symbol interference (ISI), imperfect timing synchronization, and clock jitter are all culprits. A DAC output controlled an oscillating waveform proposed to mitigate effects jitter. This architecture has additional benefit mixing impulse response energy a higher frequency, allowing high-frequency image input be used as output. potential for...

10.1109/jssc.2004.829377 article EN IEEE Journal of Solid-State Circuits 2004-08-31

A low-power CMOS reconfigurable analog-to-digital converter that can digitize signals over a wide range of bandwidth and resolution with adaptive power consumption is described. The achieves the operating by (1) reconfiguring its architecture between pipeline delta-sigma modes; (2) varying circuit parameters, such as size capacitors, length pipeline, oversampling ratio, among others; (3) bias currents opamps in proportion to sampling frequency, accomplished through use phase-locked loop...

10.1109/4.972140 article EN IEEE Journal of Solid-State Circuits 2001-01-01

This paper discusses fully digital error correction and self-calibration which correct errors due to capacitor mismatch, charge injection, comparator offsets in algorithmic A/D converters. The calibration is performed without any additional analog circuitry, the conversion does not need extra clock cycles. technique can be applied converter configurations including pipelined, cyclic, or pipelined cyclic configurations. To demonstrate concept, an experimental 2-stage implemented a standard...

10.1109/4.280701 article EN IEEE Journal of Solid-State Circuits 1994-04-01

Abstract Sulfonated fluorinated multiblock copolymers based on high performance polymers were synthesized and evaluated for use as proton exchange membranes (PEMs). The consist of fully disulfonated poly(arylene ether sulfone) partially ketone) hydrophilic hydrophobic segments, respectively. Synthesis the was achieved by a condensation coupling reaction between controlled molecular weight oligomers. could be conducted at relatively low temperatures (e.g., 105 °C) utilizing highly reactive...

10.1002/pola.23780 article EN Journal of Polymer Science Part A Polymer Chemistry 2009-11-24

Linearity errors of weighted capacitor digital-to-analog converters (DAC's) can be corrected using a simple digital algorithm. The additional circuitry required is approximately 350 gates plus 10 bytes memory space.

10.1109/tcs.1983.1085339 article EN IEEE Transactions on Circuits and Systems 1983-03-01

Abstract Context Male hypogonadism is associated with visceral obesity and the metabolic syndrome: factors important for development of nonalcoholic fatty liver disease (NAFLD). The Testosterone Trials (The T Trials) showed testosterone (T) treatment compared placebo in older hypogonadal men was decreases cholesterol insulin levels suggesting that may improve NAFLD. Objective Compare effects vs on NAFLD scores scans elderly men. Methods Secondary data analyses from 479 total < 275...

10.1210/clinem/dgad511 article EN The Journal of Clinical Endocrinology & Metabolism 2023-09-01

A fully-differential folded-cascode op amp design is presented which achieves both high dc gain and unity-gain frequency. The attained using an active cascode circuit to increase the output resistance of amplifier. In contrast previous work, gain-enhancement implemented only two amps instead four single-ended amplifiers. Implementation common mode feedback for these internal amplifiers achieved with a single device made possible due local around Simulation results indicate that technique in...

10.1109/82.279212 article EN IEEE Transactions on Circuits and Systems II Analog and Digital Signal Processing 1994-03-01

The effects of substrate noise on analog circuits in a mixed-signal chip are described and analyzed based measured results. Experimental data from 0.25-/spl mu/m CMOS test reveals that generated by digital couples into through circuit asymmetries device nonlinearity, degrading performance. In particular, delta-sigma modulator shows over 20-dB reduction signal-to-noise-plus-distortion ratio (SNDR) the presence large toggling inverters. To combat noise, technique active shaping is...

10.1109/jssc.2004.835810 article EN IEEE Journal of Solid-State Circuits 2004-10-26

We propose a new digital background calibration method for capacitor mismatches in pipelined analog-to-digital converters (ADCs). It combines commutated feedback switching with correlation loop to extract mismatch information, which is subsequently used correct errors caused by the mismatch. This an all-digital technique requiring minimal extra circuits, and applicable both single-bit multibit-per-stage architectures. Simulations 15-stage, 1.5-bit-per-stage ADC of sigma = 0.25% each stage...

10.1109/tcsii.2008.924369 article EN IEEE Transactions on Circuits & Systems II Express Briefs 2008-08-04

A two-stage microdisplay architecture using silicon light emitters and image intensification is presented. backplane IC implemented in standard 0.18-/spl mu/m CMOS technology incorporating display drivers an array of avalanche diodes produces a faint optical image, intensifier efficiently amplifies the to useful luminance levels. This can achieve adequate for projection applications high energy efficiency. The integrated includes 360 /spl times/ 200 pixel with 10b precision current-mode...

10.1109/jssc.2005.858482 article EN IEEE Journal of Solid-State Circuits 2005-12-01

An image sensor with a 2.54μm pixel fabricated in 0.18μm CMOS technology is presented. The 3T drain-side row-select reduces reset noise by cascoded feedback and increases responsivity common-source readout. 13e- the at 550nm 1.12V/lux-s source-follower readout mode 5.6V/lux-s

10.1109/isscc.2006.1696259 article EN 2006-01-01

Unlike coaxial cable, optical fiber has a bandwidth commensurate with the clock rates of even fastest rapid single flux quantum (RSFQ) circuits. Employing this advantage, we have developed an optoelectronic clocking system, in which pulses from picosecond laser are delivered via to superconducting chip, on metal-semiconductor-metal (MSM) photodiodes generate fast electrical subpicosecond timing accuracy. An pulse splitter, constructed out beamsplitters, mirrors, and half-wave plates, permits...

10.1109/77.622062 article EN IEEE Transactions on Applied Superconductivity 1997-06-01

Oversampled analog-to-digital conversion has been demonstrated to be an effective technique for high resolution (A/D) that is tolerant process imperfections. The area and power budget of conventionally designed oversampled converters precluded their application from areas where a large number low frequency signals need converted simultaneously. A new A/D design methodology proposed cut the per channel converter. implementation 16-channel converter presented which can used as core...

10.1109/4.309903 article EN IEEE Journal of Solid-State Circuits 1994-01-01

Charge-to-digital conversion offers advantages over conventional charge readout techniques because it performs digitization directly in the domain. The approach consolidates hardware, reduces power and weight, eliminates many sources of noise nonlinearity. This paper introduces an architecture for a charge-to-digital converter (CDC) that is tailored toward charge-coupled device (CCD) implementation. New methods generating charge, sensing comparing packets are described improve accuracy....

10.1109/4.545815 article EN IEEE Journal of Solid-State Circuits 1996-01-01
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