Supply voltage reduction beyond the minimum energy per operation point is advantageous for supply constrained applications, but limited by degradation of on-to-off current ratios with decreasing supply. In this work, we show that effective ratio can be considerably improved use Schmitt Trigger structures, which effectively reduce leakage from gate output node and thereby stabilize level. A method applying concept to general logic presented. Design rules concerning transistor sizing,...

Supply-voltage reduction in digital circuits beyond the minimum energy per operation point is advantageous for supply-voltage-constrained applications and can help to considerably reduce standby power consumption. Schmitt trigger (ST) logic allows ultra-low voltage (ULV) operation; hardware implementations with supply voltages as low 62mV have been demonstrated. In this paper, a systematic in-depth analysis of ST presented. First, it shown that at below ultimate limit standard CMOS circuits,...

This work presents a formulation of the FIR filter problem with sum power-of-two (POT) coefficients as mixed integer linear and solves it heuristically. The optimization is formulated to minimize number nonzero bits in each coefficient without violating specifications within pass stop bands. A novel fast efficient local search algorithm for proposed. called POTx does not use tree structure contrast conventional MILP algorithms offers computation because presorted space, monotonic dedicated...

In this paper, the authors demonstrate a standard cell-based circuit technique fully operational at supply voltages between 84 mV and 62 in 0.13 μm bulk CMOS depending on area overhead invested. Supply voltage reduction is limited by degradation of on/off current-ratio transistors with decreasing V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> , causing leakage currents through off to be same order magnitude as drive currents. The...

The design of sub-threshold circuits is especially challenging due to the massive impact process variations. These variabilities also heavily affect circuit timing, a problem only considered concerning combinational gates so far. In this paper effects variations on flip-flop timing at voltages are analyzed based extensive monte-carlo simulations. results show that usual timing-optimal definition parameters needs be replaced by reliability-driven approach. model validated for sub- and...

This paper investigates self-timed asynchronous design techniques for subthreshold digital circuits. In this voltage range extremely high voltage-dependent delay uncertainties arise which make the use of synchronous circuits rather inefficient or their reliability doubtful. Delay-line controlled face these difficulties with operation disadvantage necessary timing margins proper operation. we discuss overheads and present our approach to analysis reduction a minimum value by circuit allowing...

This brief proposes a new approach to utilizing positive-offset representation for sign-extension avoidance in shift-and-add implementation of finite-impulse response filter. Affine arithmetic is used model the excess offsets order curtail word-length (WL) expansion problem. Tighter probabilistically justified WL bounds are determined enable further offset be removed from each tap. The applicable even after redundant adders multiplier block filter have been minimized. Our simulation results...

This paper introduces a state-of-the-art design of high speed sigma delta digital to analog converter (DAC), which can be integrated into system-on-a-chip (SOC) for different communication transceivers. The operation in the circuit is very important accomplishing performance satisfy protocol specifications. therefore addresses this problem by using parallel structure radio frequency modulation at system level and redundancy coding improvement register transfer level. Due flexibility...

Despite an increasing interest in digital subthreshold circuits little research has been dedicated to timing modeling this voltage domain so far. Especially high variabilities makes proper necessary allow for the prediction of behavior and yield on path towards design automation. This paper first deals with gate characterization at sub-threshold voltages a waveform well resembling actual transistor-level waveforms is proposed. The error made abstraction step identified shown be typically...

A power-efficient narrow-band tunable digital front end (DFE) for bandpass sigma-delta (ΣΔ) analog-to-digital converters is presented. The proposed architecture introduces a new system topology, splitting the down converter into two mixers and placing cascaded integrator-comb decimation stage between mixers. first mixer quadrature that works at quarter of sampling frequency. It followed by complex with ΣΔ modulator DFE are digitally controlled. analyzed on level then synthesized in 130-nm...

This paper presents the implementation and power analysis of an efficient decimator architecture for cascaded Sigma-Delta (ΣΔ) modulators. The recombination logic modulators in general a gain error correction continuous time (CT) are integrated into first decimation stage. An appropriate filter topology is derived synthesized 0.18 μm CMOS technology using SYNOPSYS DESIGN COMPILER. consumption various blocks analyzed stimuli SOFO ΣΔ-modulator PRIMEPOWER. A comparison proposed to conventional...

A novel method for approximating filter coefficients to signed-power-of-two terms is proposed yielding a significant reduction in complexity and power consumption. Matlab toolbox named MSD-Toolbox (multi-stage decimation) was developed design optimize multi-stage decimation filters. The methodology used an example filter, which synthesized 0.13 mum CMOS technology. consumption of the structure analyzed. about 20% has been achieved 3-bit, second order lowpass sigma delta ADC stage when...

A multiplierless structure using an 8th order band pass (BP) sigma delta (Σ△) modulator for synthesizing the intermediate frequency (IF) signal is presented in this paper. fractional delay interpolation filter combining cascaded integrator-comb (CIC) and Lagrange filters used before Σ△-modulators to suppress image caused by time-interleaving IQ-paths. Closed form formulas estimating suppression ratio (ISR) of different interpolations are given. The results from numeric analysis match...

This paper introduces a novel selection criterion to choose between transposed and direct form filters for power efficient FIR polyphase decimators. Less than 5% tolerance calculated consumption using the proposed simulated results is observed. A combined architecture of decimators proposed. decimator 3 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">rd</sup> order low-pass Sigma-Delta modulator with an oversampling ratio 24 used as case study....

Despite an increasing interest in digital sub-threshold circuits little research has been dedicated to timing modeling this voltage domain so far. Especially high variabilities makes proper necessary allow for the prediction of behavior and yield on path towards design automation.This paper first deals with gate characterization at voltages a waveform well resembling actual transistor-level waveforms is proposed. The error made abstraction step identified shown be typically below...

Zusammenfassung Diese Arbeit befasst sich mit innovativen Schaltungskonzepten für integrierte Gleichrichter und Spannungskonverter energieautarke Applikationen. Dies umfasst außerdem Digitalschaltungstechnik im Sub-Threshold-Betrieb auch leistungseffiziente Funk (RF)-Module drahtloses Senden Empfangen. Die Elektronik soll dabei ausschließlich von Mikrogeneratoren, welche durch parasitäre Umgebungseinflüsse angeregt sind, versorgt werden. Da übliche Spannungsamplituden solcher Generatoren...

This paper presents a digital intermediate frequency (IF) quadrature modulator realized by single-bit band pass sigma-delta DAC, in which pair of single-bit-low-pass modulators is used to share the computation for doubling speed. Fractional-delay interpolation filters are added before adjust interleaved timing relationship between IQ paths. Carry-save algorithm increase speed both and filters, leads improvement with little area overhead. The simulation results show that proposed design can...

This paper introduces an improved method for pulse shaping filtering in a digital communication modulator. uses memory to store different waveform frames instead of the FIR filter coefficients. At run time, interpolation can be directly done by retrieving these waveforms from without any arithmetic operations which are needed conventional filter. Therefore, this takes advantage access reduce circuitry, and thus time power computations structure. Totally, N=K*L saved every input symbol...

Abstract. Eine der großen Herausforderungen beim Betrieb von Schaltungen bei extrem niedrigen Versorgungsspannungen ist die starke Zunahme des Einflusses zufälliger Prozessvariationen auf Verzögerungszeiten Gatter. Dies erfordert sehr hohe Sicherheitsmargen im Timing Schaltungen, was zu einer deutlichen Verringerung Geschwindigkeit und einem Anstieg Energie pro Operation führt. Asynchrone Schaltungstechniken, durch ihre Kodierung das Ende detektieren können, sind daher dieser Anwendung eine...

Abstract. Dieser Beitrag stellt die Implementierung eines neuartigen Ansatzes einer effizienten Dezimator-Architektur für kaskadierte Sigma-Delta Modulatoren vor. Die Rekombinationslogik kaskadierter und Korrektur des Verstärkungsfehlers zeitkontinuierlicher (CT) werden in erste Stufe Dezimators integriert. Eine entsprechende Filtertopologie wird hergeleitet auf einem Hardware-Emulator der Firma Mentor Graphics implementiert. Der Vergleich vorgeschlagenen Struktur mit herkömmlichen zeigt...