With increasing applications of silicon carbide (SiC) power MOSFETs, more attention is being paid to reliability issues, among which the long-term stability gate threshold voltage paramount importance. In this study, laboratory experiments are conducted investigate instability under AC stresses with different duty ratios, and on & off-state voltages. It found that no prominent drift would occur even for bipolar stresses, as long within (higher than) critical negative bias related device...

Silicon carbide (SiC) metal–oxide–semiconductor field-effect transistors (MOSFETs) are regarded as the key device for next generation of power electronics. However, wide applications hindered by threshold voltage instability. How drifts under both static and dynamic gate stress has been reported. But underpinning mechanism remains to be revealed, which is basis exploration application solutions. This letter investigate why drifts. It found that local electric field plays role behind...

A physical model has been developed which complies with the experimental observation on failure mechanism of ultrathin gate oxide breakdown during constant voltage stress. Dynamic equilibrium needs to be established between percolation conductive path and dielectric induced epitaxy (DBIE) formation transient. The is capable linking model, soft breakdown, hard DBIE growth for a variety stress conditions thickness without involving new empirical parameters.

For silicon carbide (SiC) power MOSFETs, threshold voltage drift is a remaining obstacle in their way to the market. This study experimentally investigates under dynamic or switching gate stresses. It shown that, beside static stress, events can themselves be driving force of drift. However, this happens only when stress bipolar. The extends show that induced sustained. findings used further work for managing and coping with device applications.

A surface passivation method to improve the film quality of HfO2 gate dielectric on Ge substrate by using ultrathin AlNx layer is reported. Results show that more effective in suppressing GeOx formation at HfO2∕Ge interface, resulting improved C–V characteristics, than nitridation-passivated devices. In addition, a thermal stability study shows promising for future metal–oxide–semiconductor

Ge-MOS devices (EOT /spl sim/7.5 Aring/, J/sub g/ sim/ 10/sup -3/ A/cm/sup 2/) are fabricated on both n- & p-type Ge-substrates, using novel surface passivation and TaN/HfO/sub 2/ gate stack. Results show that the plasma-PH/sub 3/ treatment thin AlN layer at HfO/sub 2//Ge interface effective to suppress GeO formation, which is mainly formed during deposition, prevent Ge out-diffusion, resulting in improved C-V characteristics for n-MOS device with extremely low leakage. Thermal stability...

We demonstrate enhancement of electron mobility in nMOSFET using an ultrathin pure Ge crystal channel layer directly grown on a bulk Si wafer. A thin is also top as capping layer. Using the Si/Ge/Si structure, maximum 2.2X achieved while good gate dielectric properties and junction qualities devices are maintained.

As the silicon carbide (SiC) power metal–oxide–semiconductor field-effect transistor (MOSFET) develops, increasing efforts are placed on ac bias temperature instability (AC BTI). It was reported that AC BTI becomes significant when and only gate stress is bipolar. A detailed study made in this article to reveal underpinning mechanism. physical model proposed explain how why bipolar affects threshold drift. found polarity has be carefully defined. shows, it electric field, rather than voltage...

Numerous failure mechanisms associated with hard breakdowns (HBD) in ultrathin gate oxides were physically studied high-resolution transmission electron microscope (TEM). Migration of silicide from silicided and source/drain regions, abnormal growth dielectric-breakdown-induced epitaxy (DBIE), poly-Si meltdown recrystallization, severe damage Si substrate, total substrate the entire transistor are among common microstructural damages observed metal-oxide-semiconductor field-effect...

We demonstrate high-performance Schottky CMOS transistors with NiSi source/drain and gate-all-around (GAA) silicon nanowire (~5 nm) channels. The exhibit good <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</i> <sub xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> / xmlns:xlink="http://www.w3.org/1999/xlink">off</sub> characteristics, along fully controlled shortchannel effects revealed by low drain-induced barrier lowering (~10 mV/V)...

Parallel devices in nonuniform conditions can easily lead to reduced overall reliability or even failure due uneven energy distribution. Especially under long-term avalanche stresses, the degradation of device may have a great impact on electrical parameters and performance. To study tendency aging mechanism parallel-connected silicon carbide (SiC) MOSFET, repetitive unclamped inductive switching (UIS) experiments are carried out this article. Technology computer-aided design (TCAD)...

Owing to the superior performances, silicon carbide (SiC) metal oxide semiconductor field effect transistors ( <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> s) attract a lot of attention. To increase power density, it is desired use third quadrant (3rd-quad) characteristics rather than externally paralleled Schottky diode for freewheeling during deadtime. It has been known that 3rd-quad far more body diode, and MOS channel also...

We present, <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">for</i> xmlns:xlink="http://www.w3.org/1999/xlink">the</i> xmlns:xlink="http://www.w3.org/1999/xlink">first</i> xmlns:xlink="http://www.w3.org/1999/xlink">time</i> , the monolithic integration of Gate-Ail-Around (GAA) Si-nanowire FETs into CMOS logic using top-down approach. The drive currents for N-and P-MOS transistors are matched different number channels each to obtain symmetric...

The physical dimension of the hillocks formed during gate-dielectric-breakdown-induced epitaxy (DBIE) is found to be dependent on transistor type. When narrow transistors area between 3.0×10−10 and 8.0×10−10 cm2 with a gate oxide ranging from 16 33 Å electrically stressed in inversion mode under same accelerated stress condition, DBIEs n-metal semiconductor field effect (MOSFET) are always about 2 times or more larger than that p-MOSFET. difference DBIE dimensions primarily attributed...

A comparative study on SiC MOSFETs is carried out with an emphasis the design of integrated Schottky barrier diode (SBD) numerical simulations by Sentaurus TCAD. Compared conventional MOSFET (C-MOS) and SBD-embedded (C-MOSBD), (M-MOSBD) features a hybrid doping mesa above JFET region where contact formed, which exhibits superior trade-off between on-state resistance ( R dson ) reverse transfer capacitance C rss ). Besides, in M-MOSBD renders better OFF-state junction field E Smax forward...

Abstract There are challenges to the reliability evaluation for insulated gate bipolar transistors (IGBT) on electric vehicles, such as junction temperature measurement, computational and storage resources. In this paper, a estimation approach based neural network without additional cost is proposed lifetime calculation IGBT using vehicle big data performed. The direct current (DC) voltage, operation current, switching frequency, negative thermal coefficient thermistor (NTC) inputs. And ( T...

The post-breakdown (BD) degradation of ultrathin gate oxide Si MOSFET devices is studied by electrical characterization, cross-sectional transmission electron microscopy (TEM) analysis, and theoretical simulation. It shown that can remain functional even if a physically direct short between the electrode substrate established. On other hand, device suffer from total failure while no physical damages be observed under TEM. location BD point to critical importance in determining type post-BD...

Ultrafast progressive breakdown has been observed in a TaN∕TiN metal gate metal-oxide-semiconductor field effect transistor (MOSFET) compared to polycrystalline silicon MOSFET. Physical analysis by transmission electron microscopy and electrical characterization shows that the ultrafast is likely be associated with metal-like filament formation of path. It path detrimental MOSFET lifetime.