Parameter variation in scaled technologies beyond 90nm will pose a major challenge for design of future high performance microprocessors. In this paper, we discuss process, voltage and temperature variations; their impact on circuit microarchitecture. Possible solutions to reduce the parameter variations achieve higher frequency bins are also presented.

We demonstrate a fully integrated linear regulator for multisupply voltage microprocessors implemented in 90 nm CMOS technology. Ultra-fast single-stage load regulation achieves 0.54-ns response time at 94% current efficiency. For 1.2-V input and 0.9-V output the enables mV/sub P-P/ droop 100-mA step with only small on-chip decoupling capacitor of 0.6 nF. By using PMOS pull-up transistor stage we achieved area 0.008 mm/sup 2/ minimum dropout 0.2 V 100 mA current. The 0.6-nF MOS is 0.090 2/.

Radiation-induced single event upsets (SEUs) pose a major challenge for the design of memories and logic circuits in high-performance microprocessors technologies beyond 90nm. Historically, we have considered power-performance-area trade offs. There is need to include soft error rate (SER) as another parameter. In this paper, present radiation particle interactions with silicon, charge collection effects, errors, their effect on VLSI circuits. We also discuss impact SEUs system reliability....

A 65 nm resilient circuit test-chip is implemented with timing-error detection and recovery circuits to eliminate the clock frequency guardband from dynamic supply voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CC</sub> ) temperature variations as well exploit path-activation probabilities for maximizing throughput. Two error-detection sequential (EDS) are introduced preserve capability of previous EDS designs while lowering energy...

A comparison of on-chip inductors with magnetic materials from previous studies is presented and examined. Results material integrated into a 90 nm CMOS processes are presented. The use copper metallization amorphous Co-Zr-Ta material. Inductance densities up to 1700 nH/mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> were obtained thanks inductance increases 31 times, significantly greater than previously published inductors. With...

A 45 nm microprocessor core integrates resilient error-detection and recovery circuits to mitigate the clock frequency (F <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CLK</sub> ) guardbands for dynamic parameter variations improve throughput energy efficiency. The supports two distinct designs, allowing a direct comparison of relative trade-offs. first design embeds sequential (EDS) in critical paths detect late timing transitions. In...

We demonstrate an integrated buck dc-dc converter for multi-V/sub CC/ microprocessors. At nominal conditions, the produces a 0.9-V output from 1.2-V input. The circuit was implemented in 90-nm CMOS technology. By operating at high switching frequency of 100 to 317 MHz with four-phase topology and fast hysteretic control, we reduced inductor capacitor sizes by three orders magnitude compared previously published converters. This eliminated need magnetic core enabled integration decoupling...

CMOS technology scaling is causing the channel lengths to be sub-wavelength of light. Parameter variation, caused by lithography, will pose a major challenge for design and reliability future high performance microprocessors in nanometer technologies. In this paper, we present impact these variations on processor functionality, predictability reliability. We propose CAD solutions variation tolerance. conclude paper with soft error rate trends tolerant circuits enhancement.

Temperature, voltage, and current sensors monitor the operation of a TCP/IP offload accelerator engine fabricated in 90nm CMOS, control unit dynamically changes frequency, body bias for optimum performance energy efficiency. Fast response to droops temperature is enabled by multi-PLL clocking on-chip bias. Adaptive techniques are also used compensate degradation due device aging, reducing aging guardband.

This paper presents modeling and analysis of 1T-1MTJ STT RAM memory arrays under process variations thermal disturbances. Bounds on the magnetic material design space for embedded applications are illustrated. Impact relaxed timing/area effect scaling bitcells have been evaluated.

Three circuit techniques for dynamic variation tolerance are presented: (i) Sensors with adaptive voltage and frequency circuits, (ii) Tunable replica circuits timing-error prediction error recovery, (iii) Embedded error-detection sequential recovery. These mitigate the clock guardbands variations, thus improving microprocessor performance energy-efficiency. described a focus on different trade-offs in guardband reduction design overhead. Opportunities CAD to further enhance energy...

In this paper, we present a survey of recent works in developing neuromorphic or neuro-inspired hardware systems. particular, focus on those systems which can either learn from data an unsupervised online supervised manner. We algorithms and architectures developed specially to support on-chip learning. Emphasis is placed friendly modifications standard algorithms, such as backpropagation, well novel structural plasticity, for low-resolution synapses. cover related both spike-based more...

The neutron soft error rate (SER) dependency on voltage and area was measured for a state-of-the-art 90-nm CMOS technology. SER increased by 18% 10% reduction in voltage, scaled linearly with diode area. per bit of SRAMs 0.25 /spl mu/m, 0.18 0.13 90 nm showed an increase 8% generation.

On-chip inductors with magnetic material are integrated into both advanced 130 and 90nm complementary metal-oxide semiconductor processes. The use aluminum or copper metallization amorphous CoZrTa material. Increases in inductance of up to 28 times corresponding densities 1.3 μH/mm2 were obtained, significantly greater than prior values for on-chip inductors. With such improvements, the effects eddy currents, skin effect, proximity effect become clearly visible at higher frequencies. was...

The next decade will usher in a new era of technological innovation where compute, communications, and intelligence converge. number connected devices is estimated to reach 500 billion by 2030, which 59× larger than the expected world population <xref ref-type="bibr" rid="ref1" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">[1]</xref> . Instead humans dominating use wireless networks, objects or things become dominant users. Networks incorporate...

This paper describes an experiment to characterize soft error rate of static latches for neutrons using a neutron beam, with measured rates as function diffusion collection areas and supply voltages. The also quantifies the effectiveness two promising hardening techniques scaling trends.

We designed a soft error rate (SER) tolerant latch utilizing local redundancy. implemented test chip containing both the standard and SER-tolerant latches in 90-nm dual-V/sub T/ CMOS process. Accelerated measurements with neutron beam at Los Alamos National Laboratory demonstrated 10/spl times/ better reliability of over no speed degradation. The worst case energy area penalties were 39% 44%, respectively. Both are negligible for standard-latch transistor sizes least double minimum width....

Future high performance microprocessor design with technology scaling beyond 90nm will pose two major challenges: (1) energy and power, (2) parameter variations. Design practice have to change from deterministic probabilistic statistical design. This paper discusses circuit techniques automation opportunities overcome the challenges.

We propose an on-chip 1.8 V-to-0.9 V DC-DC converter aimed to reduce the input current and decoupling requirements of future microprocessors. By utilizing a 90-nm CMOS process, employing four-phase hysteretic control, operating at ultra-high frequency 480-MHz, we achieved 10% output droop with only 2.5 nF decoupling, for 0.5 A load current. No off-chip was connected output. At 480 MHz measured efficiency 72%. 250 MHz, improved 76% cost 17% or larger 11.5 nF. 100 rating would require...

We describe various design automation solutions for migration to a dual-Vt process technology. include the results of Lagrangian Relaxation based tool, iSTATS, and heuristic iterative optimization flow. Joint allocation sizing reduces total power by 10+% compared with Vt alone, 25+% pure methods. The flow requires 5x larger computation runtime than iSTATS due its nature.

On-chip inductors with 2 levels of magnetic material were integrated into an advanced 130-nm CMOS process to obtain over order magnitude increase in inductance (19times) and Q-factor (16times), significantly greater than prior values les2.3times for high frequency inductors. The enhances at frequencies up 9.8 GHz. Measurements models the permeability from amorphous CoZrTa alloy demonstrate that skin effect eddy current dampening become important. Two high-temperature long annealing-time...

This paper reports a delay-locked loop (DLL) based hysteretic controller for high-frequency multiphase dc-dc buck converters. The DLL control employs the switching frequency of comparator as reference to automatically synchronize remaining phases and eliminate need external synchronization. A dedicated duty cycle is used enable current sharing ripple cancellation. We demonstrate four-phase converter that operates at 25-70 MHz with fast output conversion range 17.5%-80%. achieves an...

Microprocessor clock frequency (FCLK) is traditionally determined based on maximum supply voltage (Vcc) droop and temperature specifications. Since typical usage patterns usually run at nominal Vcc temperature, these infrequent dynamic variations severely limit FCLK. The concept of timing-error detection correction in previous work by Ernst, D., et al, (2003) extended implemented a test-chip 65nm CMOS Bai, P., (2004) to explore the effectiveness resilient circuits eliminating FCLK guardbands...

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> We present 2 Mb 2T PMOS gain cell macro on 65 nm logic process that has high bandwidth of 128 GBytes/sec, fast cycle time ns and 6-clock cycles access at GHz. Macro features a full-rate pipelined architecture, ground precharge bitline, non-destructive read-out, partial write support 128-row refresh to tolerate short time. Cell is 2X denser than SRAM voltage compatible with logic. </para>