This paper proposes a novel topology for optical Network on Chip (NoC) architectures with the key advantages of regularity, vertex symmetry, scalability to large scale networks, constant node degree, and simplicity. Moreover, we propose minimal deterministic routing algorithm proposed which leads small simple photonic routers. Built upon our network topology, present scalable all-optical NoC, referred as 2D-HERT, offers passive data streams based their wavelengths. Utilizing wavelength...

Nowadays, static power consumption in chip multiprocessor (CMP) is the most crucial concern of designers. Power-gating an effective approach to mitigate particularly low utilization. Network-on-Chip (NoC) as backbone multi- and many-core chips has no exception. Previous state-of-the-art techniques power-gating desire decrease alongside lack diminution performance NoC. However, maintaining utilization not yet been addressed very well. In this article, we propose TAMA (Turn-Aware Mapping &...

This article presents a new reliability-aware task mapping approach in many-core platform at design time for applications with DAG-based graphs. The main goal is to devise which meets predefined reliability threshold considering minimized performance degradation. proposed uses majority-voting replication technique fulfill error-masking capability. A quantitative model also the platform. Our homogenous architecture mesh-based interconnection using traditional deterministic XY routing...

This paper proposes a model for new reliability-aware task scheduling method hard real-time multi-core systems. The proposed is based on novel clustered replication which maintains the desired reliability threshold, minimizing both inter-core communication and redundancy overhead in network-on-chip platforms. Both single multiple errors are considered this method. Experimental results show that can schedule tasks with relatively lower latency better comparison conventional reduce execution...

Standby-sparing is one of the common techniques in order to design fault-tolerant safety-critical systems where high level reliability needed. Recently, minimization energy consumption embedded has attracted a lot concerns. Simultaneous considering and low by DVS challenging problem designing such system, since using been shown reduce profoundly. In this article, we have studied different schemes standby-sparing from point view. Moreover, propose new scheme which addresses both jointly...

This paper proposes a nanophotonic Network-on-Chip architecture based on the traditional Cube-Connected Cycles topology (CCC), which is named as ONC3. We also suggest contention-free quasi-Dimension-Order-Routing algorithm for proposed structure. Compared to previous 2D layouts, our novel scheme lessens crosstalk parameter of insertion loss and consequently, power consumption. Besides, router structure area-efficient. On other hand, optical destination checking supersedes electrical resource...

This article proposes a Semi Online Reliable Task (SORT) mapping approach to many-core platforms divided into two sections: offline and online. The section is twofolded approach. It maintains the reliability of mapped task graph against soft errors considering threshold defined by designers. As wear-out mechanisms decrease lifetime system, our proposed increases system using migration scenarios. specifies plans with minimum overhead novel heuristic SORT required level in whole replication...

Emerging nanoscale silicon-photonics with its advances in fabrication and integration of on-chip CMOS-compatible optical elements are good news for system designers. Optical Network-on-Chips (ONoCs) could be the next generation NoCs. On other hand, hybrid opto-electrical networks may provide higher bandwidth, lower latency better power dissipation when considering both electrical characteristics on multicore platforms. The cluster-based technique locally connects processing cores through...

The trade-off between power consumption and fault tolerance in embedded processors has been highlighted recent years. This paper proposes an approach to reduce the dynamic of conventional fault-tolerant techniques used register file without affecting effectiveness techniques. reduction mechanism is based on alleviating unused registers file. To evaluate proposed approach, it applied three techniques: Single-bit Error Correction-Double-bit Detection (SEC-DE D) code, duplication with parity,...

This paper presents a new reliability-aware task mapping approach in many-core platform at design time for applications with DAG-based graphs. The main goal of this is to devise scenario which meets the predefined reliability threshold ensuring minimum performance degradation. proposed uses majority-voting replication technique fulfill error-masking capability. A quantitative model also platform. Our homogenous architecture mesh-based interconnection using traditional deterministic XY...

The Automatic Modulation Classification (AMC) technique identifies the modulation scheme used in a received signal automatically without any prior knowledge or manual intervention. When multiple signals with different schemes coexist wireless communication systems, it's crucial task. In AMC, features and patterns are typically analyzed to classify into one of several predefined based on machine learning algorithms. It has been shown that deep (DL) algorithms effective AMC. Using neural...

Technology scaling, increasing number of components in a single chip, and aging effects have brought severe reliability challenges multi-core platforms. They are more susceptible to faults, both permanent transient. This paper proposes Lifetime Reliability-aware Task Mapping (LRTM) approach many-core platforms with heterogeneous cores. It tries confront transient faults wear-out failures. Our proposed maintains the predefined level for task graph presence over whole lifetime system. LRTM...

This paper presents a novel power and reliability-aware task mapping approach in many-core platforms for hard realtime applications which is called LORAP. The LORAP contrives scenario to meet the predefined reliability threshold ensuring minimum consumption overhead. It drastically decreases time complexity uses slack of running apply heuristic DVFS reduce quantitative modeling this effective failure rate based on instruction footprints obtained using new low AVF calculations algorithm....

The optical network-on-chip (ONoC) is a promising alternative to the traditional electrical network. However, in manycore systems, crosstalk noise and insertion loss significantly limit scalability of ONoCs. We propose 2 × switch composed two microring resonator-based switching elements with no waveguide crossings. Also, effects reducing power loss, due crossing elimination, on transmission spectra are investigated. measured −15 dB for through port larger than −20 drop port. An values states...

Multi/Many-core architectures will be the popular platform for future system design. Recent investigations show that hybrid optical-electrical interconnection network can an appropriate alternative to traditional electrical NoC. Undoubtedly, memory wall is one of most important challenges multi/many-core systems which somehow alleviated thanks hierarchical structure. Cache subsystem plays essential role in increasing efficiency In this paper, after exploring effect cache subsystem's...

Large Language Models (LLMs) are emerging as promising tools in hardware design and verification, with recent advancements suggesting they could fundamentally reshape conventional practices. In this survey, we analyze over 54 research papers to assess the current role of LLMs enhancing automation, optimization, innovation within verification workflows. Our review highlights LLM applications across synthesis, simulation, formal emphasizing their potential streamline development processes...