A5041342112- Radiation Effects in Electronics
- VLSI and Analog Circuit Testing
- Embedded Systems Design Techniques
- Low-power high-performance VLSI design
- Physical Unclonable Functions (PUFs) and Hardware Security
- VLSI and FPGA Design Techniques
- Parallel Computing and Optimization Techniques
- Integrated Circuits and Semiconductor Failure Analysis
- Interconnection Networks and Systems
- Reliability and Maintenance Optimization
- Distributed systems and fault tolerance
- Particle Detector Development and Performance
- Radiation Detection and Scintillator Technologies
- Advanced Fiber Optic Sensors
- CCD and CMOS Imaging Sensors
- Spacecraft Design and Technology
- Semiconductor materials and devices
- Photonic and Optical Devices
- Electrostatic Discharge in Electronics
- Software Reliability and Analysis Research
- Space Satellite Systems and Control
- Numerical Methods and Algorithms
- Real-time simulation and control systems
- Real-Time Systems Scheduling
- Graphite, nuclear technology, radiation studies
Brigham Young University
2015-2025
U.S. National Science Foundation
2019
Computing Center
2019
Sandia National Laboratories
2018
Brigham Young University - Idaho
2008-2015
Ball (France)
2013-2014
National Superconducting Cyclotron Laboratory
2014
Michigan State University
2014
National Research Nuclear University MEPhI
2014
Los Alamos National Laboratory
2009-2013
A dynamic instruction set computer (DISC) has been developed that supports demand-driven modification of its set. Implemented with partially reconfigurable FPGAs, DISC treats instructions as removable modules paged in and out through partial reconfiguration demanded by the executing program. Instructions occupy FPGA resources only when needed can be reused to implement an arbitrary number performance-enhancing application-specific instructions. further enhances functional density FPGAs...
In this paper, we argue that model-based design and platform-based are two views of the same thing. A platform is an abstraction layer in flow. For example, a core-based architecture instruction set platforms. We focus on designs induced by layer. all ASICs based particular x86 programs sets. Hence, equivalently designs. Model-based about using platforms with useful modeling properties to specify designs, then synthesizing implementations from these specifications. Hence view above (more...
This paper describes an efficient approach of applying mitigation to FPGA design protect against single event upsets (SEUs). applies selectively circuit structures depending on their importance within the design. Higher priority is given causing "persistent" errors For certain applications, selective persistent components can yield higher returns in reliability per unit cost than full mitigation. A software tool also introduced which automatically classifies based this concept and triple...
Field-programmable gate arrays (FPGAs) have been shown to provide high computational density and efficiency for many computing applications by allowing circuits be customized any application of interest. FPGAs also support programmability the circuit changed at a later time through reconfiguration. There is great interest in exploiting these benefits space other radiation environments. FPGAs, however, are very sensitive care must taken properly address effects FPGA-based systems. This paper...
Neural networks are becoming an attractive solution for automatizing vehicles in the automotive, military, and aerospace markets. Thanks to their low-cost, low-power consumption, flexibility, field-programmable gate arrays (FPGAs) among promising devices implement neural networks. Unfortunately, FPGAs also known be susceptible radiation-induced errors. In this paper, we evaluate effects of errors output correctness two [Iris Flower artificial network (ANN) Modified National Institute...
This paper investigates the viability of deploying SRAM-based FPGAs into harsh Earth-orbit environments. A reliability model is presented for estimating MTTF SRAM FPGA designs in specific orbits and orbit conditions. The requires orbit- condition-specific SEU rates design-specific estimates probability failure during a single scrubbing period. Probability are reported several from both fault-injection accelerator experiments. also includes method composite mean time to (MTTF) that...
With growing interest in the use of SRAM-based FPGAs space and other radiation environments, there is a greater need for efficient effective fault-tolerant design techniques specific to FPGAs. Triple-modular redundancy (TMR) common fault mitigation technique has been successfully demonstrated by several organizations. This technique, however, requires significant hardware resources. paper evaluates three additional compares them TMR. These include quadded logic, state machine encoding,...
SRAM-based FPGA devices are susceptible to single event effects (SEE) including upsets (SEU) within the configuration memory. Configuration scrubbing along with TMR or other hardware redundancy techniques often used mitigate of these SEUs. However, use traditional prevents ability reconfigure dynamically perform partial reconfiguration. This paper presents a novel technique that allows reconfiguration be scrubbing. A self scrubber, utilizing small portion FPGA, performs necessary operations...
The mitigation of single-event upsets (SEUs) in field-programmable gate arrays (FPGAs) is an increasingly important subject as FPGAs are used radiation environments such space. Triple modular redundancy (TMR) the most frequently SEU technique but very expensive terms area and power costs. These costs can be reduced by sacrificing some reliability applying TMR to only part FPGA design. Our partial method focuses on critical sections design increases continuous circuit. We introduce automated...
Performance benchmarks have been used over the years to compare different systems. These can be useful for researchers trying determine how changes technology, architecture, or compiler affect system's performance. No such standard exists systems deployed into high radiation environments, making it difficult assess whether in fabrication process, circuitry, software reliability sensitivity. In this paper, we propose a benchmark suite high-reliability that is designed field-programmable gate...
This study examines the single-event response of Xilinx 28 nm Kintex-7 FPGA irradiated with heavy ions. Results for effects on configuration SRAM cells, user-accessible Flip-Flop and BlockRAM™ memory are provided. also describes an unconventional single event latch-up signature observed during testing.
Low- and high-energy proton experimental data error rate predictions are presented for many bulk Si SOI circuits from the 20-90 nm technology nodes to quantify how much low-energy protons (LEPs) can contribute total on-orbit single-event upset (SEU) rate. Every effort was made predict LEP rates that conservatively high; even secondary generated in spacecraft shielding have been included analysis. Across all environments investigated, when operating within 10% of nominal voltage, LEPs were...
Extracting information about MCUs from SEU data sets can be a challenge without physical layout information. Many modern static-random access memory (SRAM) components interleave cells to improve the robustness of error-correcting codes (ECC) that detect and correct errors in array. Bit interleaving has also become popular with other large SRAM arrays, including field-programmable gate arrays (FPGAs). In this paper, we present technique for extracting statistically radiation test data....
This paper describes a FPGA configuration scrubbing approach for Xilinx 7-Series FPGAs that combines the high-speed internal available within these devices with an external scrubber. The unit continuously monitors frames of memory and corrects single-bit frame errors is used to detect multi-bit errors. Multi-bit upsets are repaired by means secondary mechanism primarily fabric. hybrid architecture scans 25,636,224 bits XC7Z020 device in several microseconds detects 8 ms then most multi-cell...
FPGAs are an appealing solution for space-based remote sensing applications. However, in a low-Earth orbit, (field programmable gate arrays) susceptible to Single-Event Upsets (SEUs). In effort understand the effects of SEUs, SEU simulator based on SLAAC-1V computing board has been developed. This artificially upsets configuration memory FPGA and measures its impact designs. The accuracy this simulation environment verified using ground-based radiation testing. tool is being used...
This paper introduces a new way to characterize the dynamic single-event upset (SEU) cross section of an FPGA design in terms its persistent and nonpersistent components. An SEU results permanent interruption service until reset. causes temporary service. These sections have been measured for several designs using fault-injection proton testing. Some applications may realize increased reliability at lower costs by focusing mitigation on just section.
High reliable reconfigurable applications today require system platforms that can easily and quickly detect correct single event upsets. This capability, however, be costly for FPGAs. paper demonstrates a technique detecting repairing SEUs within the configuration memory of Xilinx Virtex-4 FPGA using ICAP interface. The internal access port (ICAP) provides to configuring device. An application note how this used both error injection scrubbing (L. Jones, 2007). We have extended work create...
The primary goal during synthesis of digital signal processing (DSP) circuits is to minimize the hardware area while meeting a minimum throughput constraint. In field-programmable gate array (FPGA) implementations, significant savings can be achieved by using slower, more area-efficient circuit modules and/or time-multiplexing faster, larger modules. Unfortunately, manual exploration this design space impractical. paper, we introduce methodology that identifies lowest cost FPGA pipelined...
Triple Modular Redundancy (TMR) is a common reliability technique for mitigating single event upsets (SEUs) in FPGA designs operating radiation environments. For systems that employ configuration scrubbing, majority voters are needed all feedback paths to ensure proper synchronization between the TMR replicates. Synchronization voters, however, consume additional resources and impact system timing. This paper will introduce contrast four algorithms inserting while automatically performing...
Convolutional neural networks are quickly becoming viable solutions for self-driving vehicles, military, and aerospace applications. At the same time, due to their high level of design flexibility, reprogrammable capability, low power consumption, relatively cost, field-programmable gate arrays (FPGAs) very good candidates implement networks. Unfortunately, radiation-induced errors known be an issue in static random-access memory (SRAM)-based FPGAs. More specifically, we have seen that...
Convolutional neural networks (CNNs) are becoming attractive alternatives to traditional image-processing algorithms in self-driving vehicles for automotive, military, and aerospace applications. The high computational demand of state-of-the-art CNN architectures requires the use hardware acceleration on parallel devices. Field-programmable gate arrays (FPGAs) offer a great level design flexibility, low power consumption, relatively cost, which make them very good candidates efficiently...
An accelerator test was used to validate the performance of an FPGA single event upset (SEU) simulator. The Crocker Nuclear Laboratory cyclotron proton irradiate SLAAC1-V, a Xilinx Virtex board. We also SLAAC1-V as platform for configuration bitstream SEU simulator probe "sensitive bits" in various logic designs. objective experiment characterize simulator's ability predict behavior design beam during dynamic test. utilized protons at 63.3 MeV, well above saturation cross-section part....
The ability to provide flexibility and allow fine-grain circuit specialization make field programmable gate arrays (FPGA's) ideal candidates for computing elements within application-specific architectures. benefits of gate-level reconfigurability can be extended by reconfiguring resources at run-time. This technique, termed run-time reconfiguration (RTR), allows the exploitation dynamic conditions or temporal locality problems. For several applications, this technique has been shown reduce...