A5064370087- Neutrino Physics Research
- Dark Matter and Cosmic Phenomena
- Astrophysics and Cosmic Phenomena
- Particle Detector Development and Performance
- Radiation Detection and Scintillator Technologies
- Radio Frequency Integrated Circuit Design
- Particle physics theoretical and experimental studies
- Analog and Mixed-Signal Circuit Design
- Atomic and Subatomic Physics Research
- Advanced Power Amplifier Design
- CCD and CMOS Imaging Sensors
- Advanced DC-DC Converters
- Quantum, superfluid, helium dynamics
- Nuclear Physics and Applications
- Sensor Technology and Measurement Systems
- Particle accelerators and beam dynamics
- Photonic and Optical Devices
- Cold Atom Physics and Bose-Einstein Condensates
- Wireless Networks and Protocols
- Advanced NMR Techniques and Applications
- Semiconductor Lasers and Optical Devices
- Neural Networks and Applications
- Advanced Memory and Neural Computing
- Muon and positron interactions and applications
- Advancements in Semiconductor Devices and Circuit Design
Brookhaven National Laboratory
2021-2025
Brookhaven College
2024
Télécom Paris
2015-2018
IMEC
2013
Linköping University
2011
A memory polynomial (MP) based digital baseband predistorter for wideband base station RF power amplifiers is presented. The conventional predistorter's inability to sufficiently improve the adjacent channel leakage ratio (ACLR) high bandwidth signals mitigated by using a linear FIR filter. filter compensates distortions and employed prior (FIR-MP). proposed technique validated in simulations 20 MHz 80 centered at 2 GHz. PA models simulation are extracted from measurements carried out on...
This paper focuses on wideband power amplifier predistortion for current and future communications standards such as LTE 5G. As a matter of fact, the large bandwidth dynamic range exchanged signals in these make task very challenging. To overcome challenges, innovations improvements are needed three main blocks system, i.e., modeling estimation algorithms, transmission path observation path. In this work, each blocks, state art is briefly presented solutions proposed to contribute achieving...
The paper presents a reconfigurable Delta-Sigma Modulator (ΔΣM) suitable for three operation modes, whose application ranges from bio-potential signal monitoring to hearing aids. A feed-forward 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">nd</sup> -order SC ΔΣM architecture with 4-bit quantizer is selected according an analytic power optimization procedure. features programmable sampling capacitors in the first integrator and novel...
In this paper, design of an asynchronous clockless delta modulator based analog-to-digital converter (ADC) is presented. The ADC employs level-crossing sampling technique. system in the context low speed smart dust sensor applications. For benefit with continuous-time its reduced hardware and lesser quantization noise power frequency band interest. Further, unbuffered, segmented resistor-string digital-to-analog (DAC) used ADC, results component savings compared to previously reported...
A novel low-power wideband mixed-signal approach to linearize RF power amplifiers (PAs) is presented. The proposed predistorter (MSPD) based on FIR memory polynomial (FIR-MP) model, where digital filter improves the correction performance without any bandwidth expansion and MP in analog baseband provides superior linearization. MSPD avoids 5X requirement for transmitter power-hungry components when compared predistorters (DPDs) analog-RF (ARFPDs), respectively. This makes solution a very...
An event-driven, clock-free analog-to-digital converter (ADC) based on a continuous-time delta modulation technique is presented in this work. The ADC output digital datum, continuous time. system employs an unbuffered, area efficient segmented resistor-string digital-to-analog (DAC). Simulation results of the high level model 8-bit event-driven DM presented. Numbers terms component savings (number resistors and switches DAC D flip-flops bi-directional shift registers) as well comparison...
We present the optimization of Charge Sensitive Amplifier (CA) in LArASIC, a 16-channel front-end 180 nm CMOS, developed for Deep Underground Neutrino Experiment (DUNE) far detector single-phase liquid argon (LAr) time projection chamber (TPC). The charge amplification is done two stages; first (CA1) and second (CA2) stage requires small pre-biasing current (100 pA – 5 nA) or Reset Quiescent Current (RQI) sourced sunk, respectively from its input, to keep Adaptive Continuous (ACR) circuit...