A5067754429- Embedded Systems Design Techniques
- Parallel Computing and Optimization Techniques
- Real-Time Systems Scheduling
- Interconnection Networks and Systems
- Software Reliability and Analysis Research
- Advanced Memory and Neural Computing
- Neuroscience and Neural Engineering
- CCD and CMOS Imaging Sensors
- Simulation Techniques and Applications
- Neural Networks and Reservoir Computing
- Distributed systems and fault tolerance
- Spacecraft Design and Technology
- Safety Systems Engineering in Autonomy
- Formal Methods in Verification
- Radiation Effects in Electronics
- Advanced Software Engineering Methodologies
Honeywell (Czechia)
2013-2022
Czech Technical University in Prague
2020
Eindhoven University of Technology
2020
Honeywell (United States)
2013-2016
Delft University of Technology
2009-2016
Technical University of Sofia
2007
Engineers who design hard real-time embedded systems express a need for several times the performance available today while keeping safety as major criterion. A breakthrough in is expected by parallelizing applications and running them on an multi-core processor, which enables combining requirements high-performance with timing-predictable execution. parMERASA will provide timing analyzable system of parallel scalable multicore processor. goes one step beyond mixed criticality demands: It...
The EC project parMERASA (Multicore Execution of Parallelized Hard Real-Time Applications Supporting Analyzability) investigated timing-analyzable parallel hard real-time applications running on a predictable multicore processor. A pattern-supported parallelization approach was developed to ease sequential program transformation based design patterns that are timing analyzable. applied parallelize the following industrial programs: 3D path planning and stereo navigation algorithms (Honeywell...
Integrated Modular Avionics (IMA) enables incremental qualification by encapsulating avionics applications into software partitions (SWPs), as defined the ARINC 653 standard. SWPs, when running on top of single-core processors, provide robust time partitioning a means to isolate SWPs timing behavior from each other. However, moving towards parallel execution in many-core simultaneous accesses shared hardware and resources influence defying purpose isolation among applications. In this paper,...
The NimbleAI Horizon Europe project leverages key principles of energy-efficient visual sensing and processing in biological eyes brains, harnesses the latest advances <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathbf{33D}$</tex> stacked silicon integration, to create an integral sensing-processing neuromorphic architecture that efficiently accurately runs computer vision algorithms area-constrained endpoint chips. rationale behind is:...
The article represents an approach of designing multiprocessor parallel architecture based on message passing paradigm in one the Xilinx Spartan 3 family chips. Compared to Flynn's taxonomy it falls MIMD architectures with SPMD program model. Each node consist PicoBlaze -- 8-bits RISC microcontroller, local memory and communication assistant. Nodes are connected using custom-made network switch. Software abstraction model system is hierarchically designed three layers. lowest responsible for...
Abstract The CS-23 category in the General Aviation domain requires affordable, greener technologies and support single-pilot operation. CS2 COAST project addresses these needs by proposing i) a leap-change computation performance, ii) reduction of development operational costs, iii) Size, Weight, Power, Cost (SWaPC). In project, findings technological areas are packaged common platform referred as Compact Computing Platform (CCP). CCP effort is split two development-Platform Engineering...
Low energy consumption is crucial for embedded systems, including the ones that employ tiled Multiprocessor Systems-on-Chip(MPSoC). Such systems often execute real-time applications consisting of several tasks synchronized in a data-flow manner and mapped over different MPSoC tiles. Energy can be saved by lowering processor voltage frequency, hence extending application execution periods time otherwise left idle, i.e., exploiting slack. In this paper we propose framework to distribute slack...
Parallel multi-threaded applications are needed to gain advantage from multi- and many-core processors. Such processors more frequently considered for embedded hard real-time with defined timing guarantees, too. The static analysis, which is one way calculate the worst-case execution time (WCET) of parallel applications, complex time-consuming due difficulty analyze interferences threads high annotation effort resolve it.
In this paper, we address the problem of improving performance real-time embedded Multiprocessor System-on-Chip (MPSoC). Such MPSoCs often execute data-flow applications composed multiple tasks, which communicate through First-In-First-Out (FIFO) queues. The tasks on each processor in MPSoC are scheduled for execution by an instance a Real-Time Operating System (RTOS). To improve performance, propose Hardware Task-Status Manager (HWTSM) block that reduces Worst Case Execution Time (WCET)...
Full-system emulators allow the execution of guest operating systems and applications without need having access to real target hardware. For many applications, besides correct functional modeling, full-system emulator shall also be time-accurate. In this paper, we present a new multi-core simulator that delivers time-accurate preserves correctness application. The proposed solution is based on QEMU. We enriched QEMU with various time models platforms. call mcQEMU. mcQEMU supports CPUs...
In this paper, we address the problem of computing worst-case timing bound for avionics applications. The bounds are defined by application Worst-Case Execution Time (WCET). avionic applications executed on a Commercial-Of-The-Shelf (COTS)multi-core processor from embedded domain. Based identified gap in existing state-of-the-art approaches analysis, propose WOrst-case Measurement-Based stAtistical Tool (WOMBAT). proposed WOMBAT uses Extreme Value Theory (EVT). is stand-alone tool, and it...
Many modern computing platforms in the safetycritical domains are based on heterogeneous Multiprocessor System-on-Chip (MPSoC).Such expected to guarantee high-performance within a strict thermal envelope.This paper introduces testbed for and performance analysis.The allows users develop advanced scheduling resource allocation techniques aiming at finding an optimal trade-off between peak temperature achieved performance.This presents new, opensource Thermobench tool data collection analysis...
The development of avionics systems is typically a tedious and cumbersome process. In addition to the required functions, developers must consider various often conflicting non-functional requirements such as safety, performance, energy efficiency. Certainly, an integrated approach with seamless design flow that capable modelling supporting refinement down actual implementation in traceable way, may lead significant acceleration cycles. This paper presents aspect-oriented supported by tool...
The demand for high-performance computing leads to the adoption of modern Multi-Processor System-on-Chip platforms in avionics domain, where many applications are safety-critical. To fulfill safety requirements, it is vital avoid platform's overheating. In this paper, we propose a task mapping method, MultiPAWS, thermal-aware allocation safety-critical workloads under time isolation constraints. With help jointly find an optimal number scheduling windows and their lengths workload these...
In a hard Real-Time (HRT) domain such as avionics, the high application performance is important delivering predictable execution time. More precisely, defined by Worst-Case Execution Time (WCET). A common practice to boost in general purpose computing parallelisation and parallel on shared memory multicore processor. Hence, local caches, used for bridging long latency, need allow coherent accesses data. Conventional cache coherence protocols impede suitable timing analysis because of...
In this dissertation, we address the problem of performance efficient multithreading execution on heterogeneous multicore embedded systems. By systems refer to those, which have real-time requirements and consist processor tiles with General Purpose Processor (GPP), local memory, one or more coprocessors running reconfigurable logic ((e)FPGA). We improve system by combining two common methods. The first method is exploit available application parallelism means program execution. second...
This paper presents a state-of-the-art overview on how to architect, design, and optimize Deep Neural Networks (DNNs) such that performance is improved accuracy preserved. The covers set of optimizations span the entire Machine Learning processing pipeline. We introduce two types optimizations. first alters DNN model requires NN re-training, while second does not. focus GPU optimizations, but we believe presented techniques can be used with other AI inference platforms. To demonstrate...