As digital design moves into higher abstraction levels, chip-level communications become more complex, thus harder to consider low-level interconnection signal effects. Abstract interconnect models are required in order be able bring integrity issues such as crosstalk the hands of high-level system designer. Such can based on, and back-annotated from, existing fault models, which MDSI is a candidate. While MDSI, by considering RLC effects not just RC, an improvement over some other proposed...

In this article, we propose a fine-grained FPGA aging mitigation method. Our method focuses on Look Up Tables (LUTs) which Boolean functions are mapped. Based our observations, for any configuration, even if it is carefully selected, number of LUT transistors experience severe stress rates. Therefore, an algorithm presented to select several alternative configurations each LUT. Alternative obtained by input reordering. These rotationally loaded into the FPGA. Experimental results shows that...

This paper focuses on an ESL integrated environment for modeling communication channels at abstract level and providing a mechanism insertion of interconnect electrical faults into the coverage analysis. The are designed initiator-target communications have general format that contains properties found in SystemC, TLM-1 TLM-2.0 channels. presents relatively complex SystemC channel shows how our suggested crosstalk fault can be inserted lines channel. Crosstalk models examined here 1)...

Shrinking the feature size of transistors in modern integrated circuits has been led to serious timing problems. Asynchronous digital alleviate these problems some extent. The most important part as asynchronous is controlling including 33% circuit's area, approximately. In fine-grained circuits, each gate and its corresponding a pipeline stage. To decrease area overhead part, one idea clustering many possible gates single cluster with only handshaking unit. this paper two algorithms are...

In very deep sub-micrometer technology nodes, signal integrity of interconnects has been drastically jeopardized by crosstalk noise. To make a communication link reliable against faults, different detection, correction, and avoidance methods have proposed at the cost redundant spatial information overheads. this paper, we propose prediction hardware based on an abstract model deduced from low-level interconnect evaluation for new technologies. This predictor monitors data pattern to be sent...

Hardware implementation of many today's applications such as those in automotive, telecommunication, bio, and security, require heavy repeated computations, concurrency the execution these computations. These requirements are not easily satisfied by existing embedded systems. This paper proposes an system architecture that is enhanced array accelerators, a bussing enables operation accelerators. statically configurable to configure it for performing specific application. The accelerators...

Crosstalk noise has been strongly threatened the signal integrity of interconnects in new sub-micrometer technology nodes. The crosstalk prediction helps to avoid consequences. Static models cannot predict faults intensified by thermal, fab-induced, and temporal uncertainties. goal paper is use a dynamic predictor which can adapt itself presence To begin with, neural network model phenomenon would be extracted based on data transition communication wires. This implemented as an on-chip...

At the system-level, cores are put together using interconnects that we refer to as high-level communication links. This paper presents an abstract interconnect model for connecting each other estimate, and thus model, crosstalk noise resulting from physical properties of interconnects. Such models consider effects adjacent wires on in form weighted transitions. Transition weights extracted by DC analysis SPICE models. These our raw-models, which then specialized AC RLC a mixed-signal...

Nowadays electronic systems are moving toward more complex designs with various computation and communication blocks. In addition to test requirements for individual system blocks, the functionality of overall must also be tested. Conventional methods cannot satisfy this requirement due their limited scope, time cost constraints. For purpose, concept system-level (SLT)has gained attention. However, there different views on SLT in literature. Some works consider board-level testing a complete...