A5018708711- Parallel Computing and Optimization Techniques
- Embedded Systems Design Techniques
- Interconnection Networks and Systems
- Distributed and Parallel Computing Systems
- Cloud Computing and Resource Management
- Advanced Data Storage Technologies
- Hydrology and Watershed Management Studies
- Flood Risk Assessment and Management
- VLSI and Analog Circuit Testing
- Advanced Memory and Neural Computing
- Radiation Effects in Electronics
- Video Coding and Compression Technologies
- Low-power high-performance VLSI design
- Distributed systems and fault tolerance
- Real-Time Systems Scheduling
- Environmental Monitoring and Data Management
- Meteorological Phenomena and Simulations
- VLSI and FPGA Design Techniques
- Numerical Methods and Algorithms
- Graph Theory and Algorithms
- Sensor Technology and Measurement Systems
- Educational Technology in Learning
- Historical and Modern Theater Studies
- Literary and Cultural Studies
- Cultural and Mythological Studies
Forschungszentrum Jülich
2023-2024
University of Ostrava
2014-2018
VSB - Technical University of Ostrava
2014-2018
EduInnovation
2016-2017
University of Siena
2011-2012
Universitat Autònoma de Barcelona
2005-2011
Microelectronica (Romania)
2006
Developing HW modules for standard platforms like PCs or embedded devices requires a complete system emulator availability to detect and fix bugs on developed HW, Operating Systems (OS) drivers applications. This paper presents set of plug-ins an open-source CPU that enables mixed simulations between emulators hardware (HW) described in SystemC. In this three plugins QEMU are described: one connecting TLM SystemC any bus emulates, PCI PC based platform plug-in AMBA ARM platforms. With...
Network-on-Chip applications’ performance and efficiency depend on task allocation message routing, which are complex problems. In this work, we propose to use the Hungarian algorithm dynamically route messages with minimal cost, i.e. minimizing communication times while consuming least energy possible. To meet real-time constraints coming from requiring results at each flit transmission, also suggest a hardware version of it, reduces processing time by an average 42.5% respect its software...
The continuous improvements offered by the silicon technology enables integration of always increasing number cores on a single chip. Following this trend, it is expected to approach microprocessor architectures composed thousands (i.e., kilo-core architectures) in next future. To cope with demand for high performance systems, many-core designs rely integrated network-on-chips deliver correct bandwidth and latency inter-core communications. In context, simulation tools represent crucial...
The number of cores per chip keeps increasing in order to improve performance while controlling the power. According semiconductor roadmaps, future computing systems reach scale 1 Tera devices a single package. Firstly, such Tera-device will expose large amount parallelism that cannot be easily and efficiently exploited by current applications programming models. Secondly, reliability become critical issue. Finally, we need simplify design systems. TERAFLUX aims at providing framework based...
The trend to develop increasingly more intelligent systems leads directly a considerable demand for and computational power. Programming models that aid exploit the application parallelism with current multi-core exist but limitations. From this perspective, new execution are arising surpass limitations scale up number of processing elements, while dedicated hardware can help scheduling threads in many-core systems. This paper depicts data-flow based model exposes x8664 architecture millions...
The rapid evolution of Cloud-based services and the growing interest in deep learning (DL)-based applications is putting increasing pressure on hyperscalers general purpose hardware designers to provide more efficient scalable systems. infrastructures must consist energy components. take place from core infrastructure (i.e., data centers (DCs)) edges (Edge computing) adequately support new/future applications. Adaptability/elasticity one features required increase performance-to-power...
Moving from Petascale to Exascale computing necessitates optimizing the micro-architectural increase performance/power ratio of multicores (e.g., FLOPS/W). Future manycore processors will contain thousands low-powered processing elements (kilo-core Chip Multi-Processors - CMPs) support execution a large number concurrent threads. While data-driven Program eXecution Models (PXMs) are gaining popularity due they provide for thread communication, frequent data exchange among many threads puts...
Embedded multimedia devices are now a common element of our environment, such as mp3 players, handheld devices, and so on. Choosing the right main processing is key issue for success these their consumption, performance, retargetability, development time some elements that need to be analyzed well-balanced. In this paper, we map same application (MPEG-4 profile) into various target platforms generally used in embedded area. The design flow work starts with single MPEG-4 encoder description...
Future exascale machines will require multi--/ many-core architectures able to efficiently run multi-threaded applications. Data-flow execution models have demonstrated be capable of improving performance by limiting the synchronization overhead. This paper proposes augment cores with a minimalistic set hardware units and dedicated instructions that allow scheduling threads on basis data-flow principles. Experimental results show improvements system when compared other techniques (e.g.,...
In this paper we describe the implementation in SystemC of a scalable and parametrical network on chip (NoC). The NoC, with mesh topology wormhole routing, is formed resources routers connected by channels. Each router to four neighbours' through input output channels have data bus two control signals let communication based handshake. A wrapper establishes between resource its environment converting messages into format appropriated for NoC. information packed be able circulate NoC it...
This paper demonstrates the combined use of three simulation tools in support a co-design methodology for an HPC-focused System-on-a-Chip (SoC) design. The make different trade-offs between speed, accuracy and model abstraction level, are shown to be complementary. We apply MUSA trace-based simulator initial sizing vector register length, system-level cache (SLC) size memory bandwidth. It has proven very efficient at pruning design space, as its models enable sufficient without having resort...
The path towards future high performance computers requires architectures able to efficiently run multi-threaded applications. In this context, dataflow-based execution models can improve the by limiting synchronization overhead, thanks a simple producer-consumer approach. This paper advocates ISE of standard cores with small hardware extension for scheduling threads on basis dataflow principles. A set dedicated instructions allow code interact scheduler. Experimental results demonstrate...
The technology scaling towards the 10nm of silicon manufacturing, is going to introduce variability challenges, mainly due growing susceptibility thermal hot-spots and time-dependent variations (aging) in chip. consequences are two-fold: a) unpredictable performance, b) unreliable computing resources. goal HARPA project enable next-generation embedded high-performance heterogeneous many-core processors effectively address this issues, through a cross-layer approach, involving several...
Abstract Applications running in a large and complex manycore system can significantly benefit from adopting the dataflow model of computation. In execution environment, thread run only if all its required inputs are available. While potential benefits large, it is not trivial to improve resource utilization energy efficiency by focusing on models (i.e., ways specifying how threads adhering computation execute given compute/communication architecture). This paper proposes implements...
This work performs a thorough characterization and analysis of the open source Lucene search library. The article describes in detail architecture, functionality, micro-architectural behavior engine, investigates prominent online document research issues. In particular, we study how intra-server index partitioning affects response time throughput, explore potential use low power servers for search, examine sources performance degradation ands causes tail latencies. Some our main conclusions...
Transistor miniaturization, combined with the dawn of novel switching semiconductor structures, calls for careful examination variability and aging computer fabric. Time-zero time-dependent phenomena need to be carefully considered so that dependability digital systems can guaranteed. Already, architectures contain many mechanisms detect correct physically induced reliability violations. In cases, guarantees on functional correctness come at a quantifiable performance cost. The current paper...
Power consumption is a critical consideration in high performance computing systems and it becoming the limiting factor to build operate Petascale Exascale systems. When studying power of existing running HPC workloads, we find that power, energy are closely related which leads possibility optimize without sacrificing (much or at all) performance. In this paper, propose system with GNU/Linux OS Real Time Resource Manager (RTRM) aware monitors healthy platform. On system, an application for...
Future multiprocessor system-on-a-chip (MPSoC) will need high performance and low power requirements due to user demand limited battery life. In this paper, we take advantage of the architecture flexibility allowed by Network-on-Chip (NoC) build a parameterizable MPEG Compressor. compressor System has been developed in synthetizable behavioural SystemC, as flexible system divided different tiles. Each tile can be configured functional block with parameters terms power/speed/area. NoC design...
The primary objective of this study is to present techniques that cover usage a hydrodynamic model as the main tool for monitoring and assessment flood events while focusing on modelling inundation areas. We analyzed 2010 event (14th May - 20th May) occurred in Moravian-Silesian region (Czech Republic). Under investigation were four catchments: Opava, Odra, Olše Ostravice. Four models created implemented into Floreon+ platform order map areas arose during event. In dynamics water, we applied...
This paper presents tools and methodologies for dynamic allocation of high performance computing resources during operation the Floreon+ online flood monitoring prediction system. The resource is done throughout execution supported simulations to meet required service quality levels system operation. It also ensures flexible reactions changing weather situations, as it not economically feasible operate systems in full mode non-flood seasons. Different are therefore described different...
An increasing number of High-Performance Applications demand some form time predictability, in particular scenarios where correctness depends on both performance and timing requirements, the failure to meet either them is critical. Consequently, a more predictable HPC system required, particularly for an emerging class adaptive real-time applications. Here we present our runtime approach which produces results with minimized allocation hardware resources. The paper describes advantages terms...