A phase noise cancellation technique and a charge pump linearization technique, both of which are insensitive to component errors, presented demonstrated as enabling components in wideband CMOS delta-sigma fractional-N phase-locked loop (PLL). The PLL has bandwidth 460 kHz is capable 1-Mb/s in- FSK modulation at center frequencies 2402 + k MHz for = 0, 1, 2, ..., 78. For each frequency, measured results indicate that the peak spot reduction achieved by 16 dB or better, minimum suppression...

Supply-regulated phase-locked loops rely upon the VCO voltage regulator to maintain a low sensitivity supply noise and hence overall jitter. By analyzing rejection, we show that in order simultaneously meet bandwidth dropout requirements, previous implementations used supply-regulated PLLs suffer from unfavorable tradeoffs between power rejection consumption. We therefore propose compensation technique places regulator's amplifier local replica feedback loop, stabilizing by increasing while...

This paper describes the first 32 kHz low-power MEMS-based oscillator in production. The primary goal is to provide a small form-factor (1.5 × 0.8 mm 2 ) for use as crystal replacement space-constrained mobile devices. generates an output frequency of 32.768 and its binary divisors down 1 Hz. stability over industrial temperature range (-40 °C 85 °C) ±100 ppm (XO) or ±3 with optional calibration compensated (TCXO). Supply currents are 0.9 μA XO 1.0 TCXO at supply voltages from 1.4 V 4.5 V....

MEMS-based oscillators offer a silicon-based alternative to quartz-based frequency references. Here, programmable oscillator is presented which achieves better than ±0.5-ppm stability from -40 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">°</sup> C 85 and less 1-ps (rms) integrated phase noise (12 kHz 20 MHz). A key component of this system thermistor-based temperature-to-digital converter (TDC) enables accurate low compensation...

Theoretical sufficient conditions are presented that ensure the quantization noise from every constituent digital delta-sigma (DeltaSigma) modulator in a multistage DeltaSigma is asymptotically white and uncorrelated with input. The also determine if spectral shape can be imparted to dither's contribution power density of modulator's output. A large class popular modulators satisfy identified tabulated for easy reference

An analysis of the quantization noise introduced by a widely-used class single-quantizer digital delta-sigma (DeltaSigma) modulators with low-level, 1-bit dither is presented. Necessary and sufficient conditions are derived that ensure, in an asymptotic sense, various ensemble statistical properties such as uniformity independence from input delayed versions itself. The also shown to be for single realization sequence possess these time-averaged sense. Several most commonly-used DeltaSigma satisfy

This paper presents a dual-microelectromechanical system (MEMS) resonator-based temperature sensor. In this sensor, the readout circuit estimates by measuring frequency ratio of two clocks generated separate resonators with different coefficients. The is realized in 0.18-μm CMOS process and achieves resolution 20 μK over bandwidth 100 Hz while consuming 19 mW power, leading to FOM 0.04 pJK <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>...

The fundamentals and state of the art in fractional- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N</i> phase-locked-loop (PLL)-based frequency synthesis are reviewed. Particular emphasis is placed on delta-sigma PLLs quantization noise fractional spur suppression techniques for wide-bandwidth applications.

The first reported full-system 60-GHz wireless power transfer (WPT) solution that can batteryless and charge coil-free compact WPT devices is presented. system fabricated in a 40-nm digital CMOS process an inexpensive packaging material. In the rectenna (RX), grid antenna integrated with complementary cross-coupled oscillator-like rectifier. At 4-cm spacing from transmitter (TX), RX harvests energy at rate of 1.22 mW 32.8% efficiency, which significantly higher than prior state art. A novel...

Non-linear voltage-to-frequency characteristic of a voltage-controlled oscillator (VCO) severely curtails the dynamic range analog-to-digital converters (ADCs) built with VCOs. Typical approaches to enhance include embedding VCO-based ADC in ΔΣ loop or post-process digital data for calibration, both which impose significant power constraints. In contrast, this work is linearized through filtered dithering technique, wherein used as fine stage that processes residue from coarse 0-1 MASH...

In this paper, we describe the performance and power benefits of our Fine Pitch integration scheme on a Silicon Interconnect Fabric (Si IF). Here propose Simple Universal Parallel intERface (SuperCHIPS) protocol enabled by fine pitch dielet to interconnect fabric assembly. We show dramatic improvements in bandwidth, latency, are achievable through where small dielets (1-25 mm2) attached rigid (Si-IF) at (2-10 μm) short inter-die distance (50-500 using solderless metal-to-metal thermal...

Recent advances in MEMS-based oscillators have resulted their proliferation timing applications that were once exclusive to quartz-based devices [1]. For requiring low phase noise — e.g., cellular, GPS and high-speed serial links one possible approach is bias the MEMS resonator at a higher DC voltage reduce its motional impedance increase signal energy [2]. Realizing high-voltage charge pumps bulk CMOS technology limited by breakdown of well/substrate diodes shown Fig. 23.8.1(a) 23.8.1(b)....

A parallel I/O is integrated on a first-generation CELL processor in 90nm SOI CMOS. clock-tracking architecture suppresses reference jitter to achieve 6.4Gbit/s/link operation at 21.6mW/Gbit/s. effects analog circuits, particular high-speed receivers, are addressed receiver sensitivity of /spl plusmn/12mV 6.4Gbit/s with BER <10/sup -14/ measured using 7b PRBS data.

The output power level and the conversion efficiency (PCE) rate of energy-harvesting systems are vital factors in realizing effective millimeter-wave wireless transfer solutions that can battery-less charge coil-free smart everyday objects. Two 60-GHz energy harvesters use a tuned complementary cross-coupled oscillator-like rectifying circuitry 40-nm digital CMOS process presented. They harvest at rates peak PCE levels excess 1 mW 30%. These figures significantly higher than those prior art....

This paper introduces a hybrid charge pump (HCP) architecture. The HCP enables high-voltage dc outputs in nanometer-scale CMOS technology at improved power efficiency by optimally mixing different (CP) types that trade off voltage range and efficiency. Conventional CP bulk process are limited to single-diode breakdown ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\sim 12$ </tex-math></inline-formula> V...

N-path filters are finding increased prominence in recent architectures for tunable transceivers. The clock-programmable center frequency together with programmable baseband bandwidth makes it a natural fit wide programmability required software-defined radios and cognitive radios. However, the analysis of such remains difficult due to their linear periodically time-varying (LPTV) nature. This brief presents an using conversion matrices. Conversion matrices allow LPTV circuit equivalent...

Waferscale processor systems can provide the large number of cores, and memory bandwidth required by today's highly parallel workloads. One approach to building waferscale is use a chiplet-based architecture where pre-tested chiplets are integrated on passive silicon-interconnect wafer. This technology allows heterogeneous integration significant performance cost benefits. However, designing such system has several challenges as power delivery, clock distribution, waferscale-network design,...

Sensors for the perception of multimodal stimuli—ranging from five senses humans possess and beyond—have reached an unprecedented level sophistication miniaturization, raising prospect making man-made large-scale complex systems that can rival nature a reality. Artificial intelligence (AI) at edge aims to integrate such sensors with real-time cognitive abilities enabled by recent advances in AI. Such AI progress has only been achieved using massive computing power which, however, would not...

A fully integrated 60GHz CMOS PA with a PSAT of 22.6dBm is presented. To our knowledge, this the highest reported at mm-waves in standard CMOS. achieve high power level, 32 differential PAs are combined through network transmission lines, Wilkinson combiners, and multi-port argyle transformer. This method combining minimizes loss while implementing low impedance load (~12Ω) drains each last stage PAs. Electromigration other reliability issues discussed.

High-quality (Q) oscillators are notorious for being extremely slow during startup. Their long startup time increases the average power consumption in duty-cycled systems. This paper presents a novel precisely timed energy injection technique to speed up behavior of high-Q oscillators. The proposed solution is also insensitive frequency variations signal over wide enough range that makes it possible employ an integrated oscillator provide signal. A theoretical analysis carried out calculate...

A switching power amplifier (PA) architecture that offers up to 13 dB of output back-off without any drain efficiency degradation is presented. The proposed zero-voltage-switching (ZVS) contour-based PA employs a series class-E in conjunction with duty cycle modulation and tunable impedance transformation network. So-called ZVS conditions ensure ideally 100% are satisfied not just at peak power, but over the 13-dB range. Theoretical analyses losses network also presented prove actually...

An all-digital phase locked loop (ADPLL) with a proposed time-to-digital converter (TDC) which has no delay cell is designed by the 0.13- μm CMOS process. The delay-cell-less TDC (DLTDC) that can suppress device noises and PVT mismatches essential for wider bandwidth operations. Moreover, sub-gate resolution be achieved DLTDC. A ring-VCO based digitally-controlled oscillator (DCO) reduces 1/f noise also to enhance performance. 2 MHz BW ADPLL occupies 0.42 mm <sup...

In this manuscript we describe a fundamentally novel approach to the design of anti-aliasing filters. The approach, termed Filtering by Aliasing, incorporates frequency-domain aliasing operation itself into filtering task. spectral content is spread with periodic mixer and weighted simple analog filter before it aliases at sampler. By designing system according formulations presented in manuscript, sampled output will have been subjected sharp, highly programmable anti-alias filtering. This...